10
FN8208.2
September 7, 2010
Next, an Instruction Byte is issued on SDA. Bits P1
and P0 of the Instruction Byte determine which
WCR is to be written, while the WT bit determines
if the Write is to be volatile or nonvolatile. If the
Instruction Byte format is valid, another
ACKNOWLEDGE is then returned by the X9522.
Following the Instruction Byte, a Data Byte is
issued to the X9522 over SDA. The Data Byte con-
tents is latched into the WCR of the DCP on the
first rising edge of the clock signal, after the LSB
of the Data Byte (D0) has been issued on SDA (See
Figure 25).
The Data Byte determines the “wiper position”
(which FET switch of the DCP resistive array is
switched ON) of the DCP. The maximum value for
the Data Byte depends upon which DCP is being
addressed (see Table below).
Using a Data Byte larger than the values specified
above results in the “wiper terminal” being set to
the highest tap position. The “wiper position”
does NOT roll-over to the lowest tap position.
For DCP0 (64 Tap) and DCP2 (256 Tap), the Data
Byte maps one to one to the “wiper position” of
the DCP “wiper terminal”. Therefore, the Data Byte
00001111 (15
10
) corresponds to setting the “wiper
terminal” to tap position 15. Similarly, the Data
Byte 00011100 (28
10
) corresponds to setting the
“wiper terminal” to tap position 28. The mapping
of the Data Byte to “wiper position” data for DCP1
(100 Tap), is shown in “APPENDIX 1”. An example
of a simple C language function which “trans-
lates” between the tap position (decimal) and the
Data Byte (binary) for DCP1, is given in “APPEN-
DIX 2” .
It should be noted that all writes to any DCP of the
X9522 are random in nature. Therefore, the Data
Byte of consecutive write operations to any DCP
can differ by an arbitrary number of bits. Also, set-
ting the bits P1=1, P0=1 is a reserved sequence,
and will result in no ACKNOWLEDGE after send-
ing an Instruction Byte on SDA.
The factory default setting of all “wiper position”
settings is with 00h stored in the NVM of the DCPs.
This corresponds to having the “wiper teminal”
R
WX
(x = 0,1,2) at the “lowest” tap position, There-
fore, the resistance between
R
WX
and R
LX
is a min-
imum (essentially only the Wiper Resistance,
R
W
).
DCP Read Operation
A read of DCPx (x = 0,1,2) can be performed using
the three byte random read command sequence
shown in Figure 10.
The master issues the START condition and the
Slave Address Byte 10101110 which specifies that
a “dummy” write” is to be conducted. This
“dummy” write operation sets which DCP is to be
read (in the preceding Read operation). An
ACKNOWLEDGE is returned by the X9522 after the
Slave Address if received correctly. Next, an
Instruction Byte is issued on SDA. Bits P1-P0 of
the Instruction Byte determine which DCP “wiper
position” is to be read. In this case, the state of the
WT bit is “don’t care”. If the Instruction Byte for-
mat is valid, then another ACKNOWLEDGE is
returned by the X9522.
P1- P0 DCPx # Taps Max. Data Byte
00 x = 0 64 3Fh
0 1 x = 1 100 Refer to Appendix 1
1 0 x = 2 256 FFh
1 1 Reserved
X9522
