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X9522V20I-B

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
4
FN8208.2
September 7, 2010
PIN ASSIGNMENT
Pin Name Function
1
R
H2
Connection to end of resistor array for (the 256 Tap) DCP 2.
2
R
w2
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
3
R
L2
Connection to other end of resistor array for (the 256 Tap) DCP 2.
4V3
V3 Voltage Monitor Input. V3 is the input to a non-inverting voltage comparator circuit. When the V3
input is higher than the
V
TRIP3
threshold voltage, V3RO makes a transition to a HIGH level. Connect
V3 to V
SS
when not used.
5V3RO
V3 RESET Output. This open drain output makes a transition to a HIGH level when V3 is greater than
V
TRIP3
and goes LOW when V3 is less than V
TRIP3
. There is no delay circuitry on this pin. The V3RO
pin requires the use of an external “pull-up” resistor.
7WP
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write Protection is
enabled. In the enabled state, this pin prevents all nonvolatile “write” operations. Also, when the Write
Protection is enabled, and the DCP Write Lock feature is active (i.e. the DCP Write Lock bit is set to
“1”), then no “write” (volatile or nonvolatile) operations can be performed in the device (including the
wiper position of any of the integrated Digitally Controlled Potentiometers (DCPs). The WP pin uses an
internal “pull-down” resistor, thus if left floating the write protection feature is disabled.
8SCL
Serial Clock. This is a TTL level compatible input pin used to control the serial bus timing for data input
and output.
9SDA
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and out of the
device. The SDA pin input buffer is always active (not gated). This pin requires an external pull up re-
sistor.
10 Vss Ground.
11
R
L1
Connection to other end of resistor for (the 100 Tap) DCP 1.
12
R
w1
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1.
13
R
H1
Connection to end of resistor array for (the 100 Tap) DCP 1.
14
R
H0
Connection to end of resistor array for (the 64 Tap) Digitally Controlled Potentiometer (DCP) 0.
15
R
W0
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 0.
16
R
L0
Connection to the other end of resistor array for (the 64 Tap) DCP 0.
17 V2
V2 Voltage Monitor Input. V2 is the input to a non-inverting voltage comparator circuit. When the V2
input is greater than the
V
TRIP2
threshold voltage, V2RO makes a transition to a HIGH level. Connect
V2 to V
SS
when not used.
18 V2RO
V2 RESET Output. This open drain output makes a transition to a HIGH level when V2 is greater than
V
TRIP2
, and goes LOW when V2 is less than V
TRIP2
. There is no power-up reset delay circuitry on this
pin. The V2RO pin requires the use of an external “pull-up” resistor.
20 Vcc / V1 Supply Voltage.
6, 19 NC No Connect.
X9522
5
FN8208.2
September 7, 2010
PRINCIPLES OF OPERATION
SERIAL INTERFACE
Serial Interface Conventions
The device supports a bidirectional bus oriented
protocol. The protocol defines any device that
sends data onto the bus as a transmitter, and the
receiving device as the receiver. The device con-
trolling the transfer is called the master and the
device being controlled is called the slave. The
master always initiates data transfers, and pro-
vides the clock for both transmit and receive oper-
ations. Therefore, the X9522 operates as a slave in
all applications.
Serial Clock and Data
Data states on the SDA line can change only while
SCL is LOW. SDA state changes while SCL is
HIGH are reserved for indicating START and STOP
conditions. See Figure 1. On power-up of the
X9522, the SDA pin is in the input mode.
Serial Start Condition
All commands are preceded by the START condi-
tion, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The device continuously moni-
tors the SDA and SCL lines for the START condi-
tion and does not respond to any command until
this condition has been met. See Figure 2.
Serial Stop Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of
SDA while SCL is HIGH. The STOP condition is also
used to place the device into the Standby power
mode after a read sequence. A STOP condition can
only be issued after the transmitting device has
released the bus. See Figure 2.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software conven-
tion used to indicate a successful data transfer. The
transmitting device, either master or slave, will
release the bus after transmitting eight bits. During
the ninth clock cycle, the receiver will pull the SDA
line LOW to ACKNOWLEDGE that it received the
eight bits of data. Refer to Figure 3.
The device will respond with an ACKNOWLEDGE
after recognition of a START condition if the cor-
rect Device Identifier bits are contained in the
Slave Address Byte. If a write operation is
selected, the device will respond with an
ACKNOWLEDGE after the receipt of each subse-
quent eight bit word.
In the read mode, the device will transmit eight
bits of data, release the SDA line, then monitor the
line for an ACKNOWLEDGE. If an ACKNOWLEDGE
is detected and no STOP condition is generated by
the master, the device will continue to transmit
data. The device will terminate further data trans-
missions if an ACKNOWLEDGE is not detected.
The master must then issue a STOP condition to
place the device into a known state.
SCL
SDA
Data Stable Data Change Data Stable
Figure 1. Valid Data Changes on the SDA Bus
SCL
SDA
Start Stop
Figure 2. Valid Start and Stop Conditions
X9522
6
FN8208.2
September 7, 2010
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
The user addressable internal components of the
X9522 can be split up into two main parts:
—Three Digitally Controlled Potentiometers (DCPs)
—Control and Status (CONSTAT) Register
Depending upon the operation to be performed
on each of these individual parts, a 1, 2 or 3 Byte
protocol is used. All operations however must
begin with the Slave Address Byte being issued
on the SDA pin. The Slave address selects the
part of the X9522 to be addressed, and specifies
if a Read or Write operation is to be performed.
It should be noted that in order to perform a write
operation to a DCP, the Write Enable Latch (WEL)
bit must first be set.
Slave Address Byte
Following a START condition, the master must
output a Slave Address Byte (Refer to Figure 4.).
This byte consists of three parts:
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9522.
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 111 internally selects
the DCP structures in the X9522. The CONSTAT Reg-
ister may be selected using the Internal Device
Address 010.All other bit combinations are
RESERVED.
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W
bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W
bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
SCL
from
Master
Data Output
from
Transmitter
Data Output
from
Receiver
81 9
Start Acknowledge
Figure 3. Acknowledge Response From Receiver
SCL
from
Master
SA6SA7
SA5
SA3 SA2
SA1
SA0
DEVICE TYPE
IDENTIFIER
READ /
SA4
Internal Address
(SA3 - SA1)
Internally Addressed
Device
010
CONSTAT Register
111
DCP
Others
RESERVED
Bit SA0 Operation
0WRITE
1 READ
R/W
Figure 4. Slave Address Format
101 0
WRITE
ADDRESS
INTERNAL
DEVICE
X9522
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

X9522V20I-B

Mfr. #:
Buy X9522V20I-B
Manufacturer:
Renesas / Intersil
Description:
IC TRIPL DCP LASER CNTRL 20TSSOP
Lifecycle:
New from this manufacturer.
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