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X9522V20I-B

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
22
FN8208.2
September 7, 2010
D.C. OPERATING CHARACTERISTICS
Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200nS after a STOP ending a read operation; or t
WC
after a STOP ending a write operation.
Notes: 2.The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; t
WC
after a STOP that initiates
a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave Address
Byte.
Notes: 3.Current through external pull up resistor not included.
Notes: 4.V
IN
= Voltage applied to input pin.
Notes: 5.V
OUT
= Voltage applied to output pin.
Notes: 6.See Ordering Information on page 2.
Notes: 7.V
IL
Min. and V
IH
Max. are for reference only and are not tested.
Symbol Parameter Min Typ Max Unit Test Conditions / Notes
I
CC1
(1)
Current into Vcc / V1 Pin
(X9522: Active)
Read memory array
(3)
Write nonvolatile memory
0.4
1.5
mA
f
SCL
= 400kHz
I
CC2
(2)
Current into Vcc / V1 Pin
(X9522:Standby)
With 2-Wire bus activity
(3)
No 2-Wire bus activity
50
50
μA
V
SDA
= Vcc / V1
WP = Vss or Open/Floating
V
SCL
= Vcc / V1
(when no bus ac-
tivity else f
SCL
= 400kHz)
I
LI
Input Leakage Current (SCL, SDA)
0.1 10 μA
V
IN
(4)
= GND to Vcc / V1
.
Input Leakage Current (WP)
10 μA
I
ai
Analog Input Leakage 1 10 µA
V
IN
= V
SS
to V
CC
with all other an-
alog pins floating
I
LO
Output Leakage Current (SDA, V2RO,
V3RO)
0.1 10 μA
V
OUT
(5)
= GND to Vcc / V1
.
X9522 is in Standby
(2)
V
TRIPxPR
V
TRIPx
Programming Range (x = 1,2)
1.8 4.70 V
V
TRIP1
(6)
Pre - programmed V
TRIP1
threshold
1.65
2.85
1.8
3.0
1.85
3.05
V
Factory shipped default option A
Factory shipped default option B
V
TRIP2
(6)
Pre - programmed V
TRIP2
threshold
1.65
2.85
1.8
3.0
1.85
3.05
V
Factory shipped default option A
Factory shipped default option B
I
Vx
V2 Input leakage current
V3 Input leakage current
1
1
μA
V
SDA
= V
SCL
= Vcc / V1
Others = GND or Vcc / V1
V
IL
(7)
Input LOW Voltage (SCL, SDA, WP) -0.5 0.8 V
V
IH
(7)
Input HIGH Voltage (SCL,SDA, WP) 2.0
Vcc / V1
+0.5
V
V
OLx
V2RO, V3RO, SDA Output Low Voltage 0.4 V
I
SINK
= 2.0mA
X9522
23
FN8208.2
September 7, 2010
A.C. CHARACTERISTICS (See Figure 20, Figure 21, Figure 22)
A.C. TEST CONDITIONS
NONVOLATILE WRITE CYCLE TIMING
CAPACITANCE (T
A
= 25°C, F = 1.0 MHZ, VCC / V1 = 5V)
Notes: 1. Typical values are for T
A
= 25°C and Vcc / V1 = 5.0V
Notes: 2.Cb = total capacitance of one bus line in pF.
Notes: 3.Over recommended operating conditions, unless otherwise specified
Notes: 4.t
WC
is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Notes: 5.This parameter is not 100% tested.
Symbol Parameter
400kHz
Min Max Units
f
SCL
SCL Clock Frequency
0 400 kHz
t
IN
(5)
Pulse width Suppression Time at inputs
50 ns
t
AA
(5)
SCL LOW to SDA Data Out Valid
0.1 0.9
μs
t
BUF
(5)
Time the bus free before start of new transmission
1.3
μs
t
LOW
Clock LOW Time
1.3
μs
t
HIGH
Clock HIGH Time
0.6
μs
t
SU:STA
Start Condition Setup Time
0.6
μs
t
HD:STA
Start Condition Hold Time
0.6
μs
t
SU:DAT
Data In Setup Time
100 ns
t
HD:DAT
Data In Hold Time
0
μs
t
SU:STO
Stop Condition Setup Time
0.6
μs
t
DH
(5)
Data Output Hold Time
50 ns
t
R
(5)
SDA and SCL Rise Time
20 +.1Cb
(2)
300 ns
t
F
(5)
SDA and SCL Fall Time
20 +.1Cb
(2)
300 ns
t
SU:WP
WP Setup Time
0.6
μs
t
HD:WP
WP Hold Time
0
μs
Cb
(5)
Capacitive load for each bus line
400 pF
Input Pulse Levels 0.1Vcc to 0.9Vcc
Input Rise and Fall Times 10ns
Input and Output Timing Levels 0.5Vcc
Output Load See Figure 18
Symbol Parameter Min. Typ.(1) Max. Units
t
WC
(4)
Nonvolatile Write Cycle Time 5 10 ms
Symbol Parameter Max Units Test Conditions
C
OUT
(5)
Output Capacitance (SDA, V2RO, V3RO) 8 pF
V
OUT
= 0V
C
IN
(5)
Input Capacitance (SCL, WP) 6 pF
V
IN
= 0V
X9522
24
FN8208.2
September 7, 2010
POTENTIOMETER CHARACTERISTICS
Notes: 1. Power Rating between the wiper terminal R
WX(n)
and the end terminals R
HX
or R
LX
- for ANY tap position n, (x = 0,1,2).
Notes: 2.Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance = (R
wx(n)
(actual) - R
wx(n)
(expected)) = ±1 Ml
Maximum (x = 0,1,2).
Notes: 3.Relative Linearity is a measure of the error in step size between taps = R
Wx(n+1)
- [R
wx(n)
+ Ml] = ±1 Ml (x = 0,1,2)
Notes: 4.1 Ml = Minimum Increment = R
TOT
/ (Number of taps in DCP - 1).
Notes: 5.Typical values are for T
A
= 25°C and nominal supply voltage.
Notes: 6.This parameter is periodically sampled and not 100% tested.
Symbol Parameter
Limits
Test Conditions/NotesMin. Typ. Max. Units
R
TOL
End to End Resistance Tolerance -20 +20 %
V
RHx
R
H
Terminal Voltage (x = 0,1,2)
Vss
Vcc /
V1
V
V
RLx
R
L
Terminal Voltage (x = 0,1,2)
Vss
Vcc /
V1
V
P
R
Power Rating
(1)(6
)
10 mW
R
TOTAL
= 10kΩ (DCP0,
DCP1)
5mW
R
TOTAL
= 100kΩ (DCP2)
R
W
DCP Wiper Resistance
200 400 Ω
I
W
= 1mA, Vcc / V1 = 5 V,
V
RHx
=Vcc / V1, V
RLx
= Vss
(x = 0,1,2).
400 1200 Ω
I
W
= 1mA, Vcc / V1 = 2.7 V,
V
RHx
= Vcc / V1, V
RLx
= Vss
(x = 0,1,2)
I
W
Wiper Current
(6)
4.4 mA
Noise
mV/
sqt(Hz)
R
TOTAL
= 10kΩ (DCP0,
DCP1)
mV/
sqt(Hz)
R
TOTAL
= 100kΩ (DCP2)
Absolute Linearity
(2)
-1 +1
MI
(4)
R
w(n)(actual)
- R
w(n)(expected)
Relative Linearity
(3)
-1 +1
MI
(4)
R
w(n+1)
- [R
w(n) + MI
]
R
TOTAL
Temperature Coefficient
±300 ppm/°C
R
TOTAL
= 10kΩ (DCP0,
DCP1)
±300 ppm/°C
R
TOTAL
= 100kΩ (DCP2)
C
H
/C
L
/C
W
Potentiometer Capacitances
10/10/25
pF
See Figure 19.
t
wr
Wiper Response time
(6)
200
μs
See Figure 25.
V
TRIP
Vcc / V1 power-up DCP recall
threshold
V
t
PU
Vcc / V1 power-up DCP recall delay
time
(6)
25 50 75
ms
X9522
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X9522V20I-B

Mfr. #:
Buy X9522V20I-B
Manufacturer:
Renesas / Intersil
Description:
IC TRIPL DCP LASER CNTRL 20TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
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