1
Features
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
128-byte Page Mode Only for Write Operations
Low-voltage and Standard-voltage Operation
2.7 (V
CC
= 2.7V to 5.5V)
1.8 (V
CC
= 1.8V to 5.5V)
10 MHz (5V), 5MHz (2.7V) and 2 MHz (1.8V) Clock Rate
Block Write Protection
Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
both Hardware and Software Data Protection
High Reliability
Endurance: 100K Write Cycles
Data Retention: >40 Years
8-lead PDIP, 8-lead EIAJ SOIC, 16-lead JEDEC SOIC, 8-lead Leadless Array Package,
and 8-lead SOIC Array Package (SAP)
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The AT25HP256/512 provides 262,144/524,288 bits of serial electrically erasable pro-
grammable read only memory (EEPROM) organized as 32,768/65,536 words of 8-bits
each. The device is optimized for use in many industrial and commercial applications
where high-speed, low-power, and low-voltage operation are essential. The
AT25HP256/512 is available in a space saving 8-lead PDIP (AT25HP256/512), 8-lead
EIAJ SOIC (AT25HP256), 16-lead JEDEC SOIC (AT25HP512), 8-lead Leadless Array
(AT25HP256/512) package, and 8-lead SOIC Array package (SAP). In addition, the
entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
Table 1. Pin Configurations
Pin Name Function
CS
Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
VCC Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
Rev. 1113L–SEEPR–3/06
SPI Serial
EEPROMs
256K (32,768 x 8)
512K (65,536 x 8)
AT25HP256
(1)
AT25HP512
Note: 1. Not recommended for
new design; please refer to
AT25256A datasheet.
8-lead SOIC
CS
SCK
SO
WP
HOLD
GND
VCC
1
2
3
4
8
7
6
5
SI
8-lead PDIP
CS
SCK
SO
WP
HOLD
GND
VCC
1
2
3
4
8
7
6
5
SI
CS
SCK
SO
WP
HOLD
GND
VCC
1
2
3
4
8
7
6
5
SI
8-lead Leadless Array
Bottom View
HOLD
SCK
SI
VCC
CS
SO
WP
GND
1
2
3
4
5
6
7
8
16-lead SOIC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CS
SO
NC
NC
NC
NC
WP
GND
VCC
HOLD
NC
NC
NC
NC
SCK
SI
8-lead SOIC Array Package
(SAP)
Bottom View
HOLD
SCK
SI
VCC
CS
SO
WP
GND
1
2
3
4
5
6
7
8
2
AT25HP256/512
1113L–SEEPR–3/06
The AT25HP256/512 is enabled through the Chip Select pin (CS) and accessed via a 3-
wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK). All programming cycles are completely self-timed, and no separate erase
cycle is required before write.
Block Write protection is enabled by programming the status register with top ¼, top ½
or entire array of write protection. Separate Program Enable and Program Disable
instructions are provided for additional data protection. Hardware data protection is pro-
vided via the WP
pin to protect against inadvertent write attempts to the status register.
The HOLD
pin may be used to suspend any serial communication without resetting the
serial sequence.
Figure 1. Block Diagram
Absolute Maximum Ratings*
Operating Temperature..................................–55°C to +125°C
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground ....................................–1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
32,768/65,536 x 8
3
AT25HP256/512
1113L–SEEPR–3/06
Note: 1. This parameter is characterized and is not 100% tested.
Note: 1. V
IL
and V
IH
max are reference only and are not tested.
Table 2. Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0V (unless otherwise noted)
Symbol Test Conditions Max Units Conditions
C
OUT
Output Capacitance (SO) 8 pF V
OUT
= 0V
C
IN
Input Capacitance (CS, SCK, SI, WP, HOLD)6pFV
IN
= 0V
Table 3. DC Characteristics
Applicable over recommended operating range from: T
AI
= 40°C to +85°C, V
CC
= +1.8V to +5.5V,
T
AC
= 0°C to +70°C, V
CC
= +1.8V to +5.5V (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
V
CC1
Supply Voltage 1.8 3.6 V
V
CC2
Supply Voltage 2.7 5.5 V
V
CC3
Supply Voltage 4.5 5.5 V
I
CC1
Supply Current V
CC
= 5.0V at 5 MHz, SO = Open Read 6.0 10.0 mA
I
CC2
Supply Current V
CC
= 5.0V at 5 MHz, SO = Open Write 4.0 7.0 mA
I
SB1
Standby Current V
CC
= 1.8V, CS = V
CC
0.1 2.0 µA
I
SB2
Standby Current V
CC
= 2.7V, CS = V
CC
0.2 2.0 µA
I
SB3
Standby Current V
CC
= 5.0V, CS = V
CC
2.0 5.0 µA
I
IL
Input Leakage V
IN
= 0V to V
CC
–3.0 3.0 µA
I
OL
Output Leakage V
IN
= 0V to V
CC
, T
AC
= 0°C to 70°C –3.0 3.0 µA
V
IL
(1)
Input Low Voltage –0.6 V
CC
x 0.3 V
V
IH
(1)
Input High Voltage V
CC
x 0.7 V
CC
+ 0.5 V
V
OL1
Output Low Voltage
4.5V V
CC
5.5V
I
OL
= 3.0 mA 0.4 V
V
OH1
Output High Voltage I
OH
= –1.6 mA V
CC
– 0.8 V
V
OL2
Output Low Voltage
1.8V V
CC
3.6V
I
OL
= 0.15 mA 0.2 V
V
OH2
Output High Voltage I
OH
= –100 µA V
CC
– 0.2 V

AT25HP512C1-10CI-1.8

Mfr. #:
Manufacturer:
Description:
IC EEPROM 512K SPI 10MHZ 8LAP
Lifecycle:
New from this manufacturer.
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