9
AT25HP256/512
1113L–SEEPR–3/06
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25HP256/512 is divided into four array seg-
ments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected.
Any of the data within any selected segment will therefore be READ only. The block
write protection levels and corresponding status register control bits are shown in Table
8.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties
and functions as the regular memory cells (e.g., WREN, t
WC
, RDSR).
The WRSR instruction also allows the user to enable or disable the write protect (WP
)
pin through the use of the write protect enable (WPEN) bit. Hardware write protection is
enabled when the WP
pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP
pin is high or the WPEN bit is “0.” When the device is hard-
ware write protected, writes to the status register, including the block protect bits and the
WPEN bit, and the block-protected sections in the memory array are disabled. Writes
are only allowed to sections of the memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to
“0” as long as the WP
pin is held low.
Table 7. Read Status Register Bit Definition
Bit Definition
Bit 0 (RDY
)
Bit 0 = “0” (RDY
) indicates the device is ready. Bit 0 = “1” indicates the write
cycle is in progress.
Bit 1 (WEN)
Bit 1= “0” indicates the device is not write-enabled. Bit 1 = “1” indicates the
device is write-enabled.
Bit 2 (BP0) See Table 8.
Bit 3 (BP1) See Table 8.
Bits 4-6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 9.
Bits 0-7 are “1”s during an internal write cycle.
Table 8. Block Write Protect Bits
Level
Status Register Bits Array Addresses Protected
BP1 BP0 AT25HP256/512
0 0 0 None
1(1/4) 0 1 6000 - 7FFF/C000 - FFFF
2(1/2) 1 0 4000 - 7FFF/8000 - FFFF
3(All) 1 1 0000 - 7FFF/0000 - FFFF
Table 9. WPEN Operation
WPEN WP WEN ProtectedBlocks UnprotectedBlocks Status Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
