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AT25HP512C1-10CI-1.8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
4
AT25HP256/512
1113L–SEEPR–3/06
Table 4. AC Characteristics
Applicable over recommended operating range from T
A
= –40°C to +85°C, V
CC
= As Specified,
C
L
= 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol Parameter Voltage Min Max Units
f
SCK
SCK Clock Frequency
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
0
0
0
10
5
2
MHz
t
RI
Input Rise Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
2
2
2
µs
t
FI
Input Fall Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
2
2
2
µs
t
WH
SCK High Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
40
80
200
ns
t
WL
SCK Low Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
40
80
200
ns
t
CS
CS High Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
50
100
250
ns
t
CSS
CS Setup Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
50
100
250
ns
t
CSH
CS Hold Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
50
100
250
ns
t
SU
Data In Setup Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
12
20
50
ns
t
H
Data In Hold Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
10
20
50
ns
t
HD
Hold Setup Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
25
50
100
ns
t
CD
Hold Hold Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
25
50
100
ns
t
V
Output Valid
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
0
0
0
40
80
200
ns
t
HO
Output Hold Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
0
0
0
ns
t
LZ
Hold to Output Low Z
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
0
0
0
100
200
300
ns
5
AT25HP256/512
1113L–SEEPR–3/06
Note: 1. This parameter is characterized and is not 100% tested.
t
HZ
Hold to Output High Z
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
100
200
300
ns
t
DIS
Output Disable Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
100
100
250
ns
t
WC
Write Cycle Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
10
10
10
ms
Endurance
(1)
5.0V, 25°C, Page Mode
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
100K Write Cycles
Table 4. AC Characteristics (Continued)
Applicable over recommended operating range from T
A
= –40°C to +85°C, V
CC
= As Specified,
C
L
= 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol Parameter Voltage Min Max Units
6
AT25HP256/512
1113L–SEEPR–3/06
Serial Interface
Description
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25HP256/512
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25HP256/512 has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS
going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25HP256/512, and the serial output pin (SO) will remain in a high impedance state
until the falling edge of CS
is detected again. This will reinitialize the serial
communication.
CHIP SELECT: The AT25HP256/512 is selected when the CS
pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the SO will remain in
a high impedance state.
HOLD: The HOLD
pin is used in conjunction with the CS pin to select the
AT25HP256/512. When the device is selected and a serial sequence is underway,
HOLD
can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD
pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD
pin is brought high while the
SCK pin is low (SCK may still toggle during HOLD
). Inputs to the SI pin will be ignored
while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP
) will allow normal read/write operations
when held high. When the WP
pin is brought low and WPEN bit is “1”, all write opera-
tions to the status register are inhibited. WP
going low while CS is still low will interrupt a
write to the status register. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the status register. The WP pin
function is blocked when the WPEN bit in the status register is “0”. This will allow the
user to install the AT25HP256/512 in a system with the WP
pin tied to ground and still
be able to write to the status register. All WP
pin functions are enabled when the WPEN
bit is set to “1”.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AT25HP512C1-10CI-1.8

Mfr. #:
Buy AT25HP512C1-10CI-1.8
Manufacturer:
Description:
IC EEPROM 512K SPI 10MHZ 8LAP
Lifecycle:
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