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FM28V202A-TGTR

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FM28V202A
2-Mbit (128 K × 16) F-RAM Memory
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-90309 Rev. *F Revised August 12, 2015
2-Mbit (128 K × 16) F-RAM Memory
Features
■ 2-Mbit ferroelectric random access memory (F-RAM) logically
organized as 128 K × 16
❐ Configurable as 256 K × 8 using UB and LB
❐ High-endurance 100 trillion (10
14
) read/writes
❐ 151-year data retention (see the Data Retention and
Endurance table)
❐ NoDelay™ writes
❐ Page mode operation to 30-ns cycle time
❐ Advanced high-reliability ferroelectric process
■ SRAM compatible
❐ Industry-standard 128 K × 16 SRAM pinout
❐ 60-ns access time, 90-ns cycle time
■ Advanced features
❐ Software-programmable block write-protect
■ Superior to battery-backed SRAM modules
❐ No battery concerns
❐ Monolithic reliability
❐ True surface mount solution, no rework steps
❐ Superior for moisture, shock, and vibration
■ Low power consumption
❐ Active current 7 mA (typ)
❐ Standby current 120 A (typ)
■ Low-voltage operation: V
DD
= 2.0 V to 3.6 V
■ Industrial temperature: –40 C to +85 C
■ 44-pin thin small outline package (TSOP) Type II
■ Restriction of hazardous substances (RoHS) compliant
Functional Overview
The FM28V202A is a 128 K × 16 nonvolatile memory that reads
and writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM28V202A operation is similar to that of other RAM
devices and therefore, it can be used as a drop-in replacement
for a standard SRAM in a system. Read cycles may be triggered
by CE
or simply by changing the address and write cycles may
be triggered by CE or WE. The F-RAM memory is nonvolatile
due to its unique ferroelectric memory process. These features
make the FM28V202A ideal for nonvolatile memory applications
requiring frequent or rapid writes.
The device is available in a 400-mil, 44-pin TSOP-II surface
mount package. Device specifications are guaranteed over the
industrial temperature range –40 °C to +85 °C.
For a complete list of related documentation, click here.
Address Latch & Write Protect
CE
Control
Logic
WE
Block & Row Decoder
A
I/O Latch & Bus Driver
OE
DQ
16 K x 16 block 16 K x 16 block
16 K x 16 block 16 K x 16 block
16 K x 16 block 16 K x 16 block
16 K x 16 block 16 K x 16 block
A
. . .
Column Decoder
. . .
UB, LB
ZZ
16-0
16-2
A
1-0
15-0
Logic Block Diagram
FM28V202A
Document Number: 001-90309 Rev. *F Page 2 of 22
Contents
Pinout ................................................................................3
Pin Definitions ..................................................................3
Device Operation ..............................................................4
Memory Operation .......................................................4
Read Operation ...........................................................4
Write Operation ...........................................................4
Page Mode Operation .................................................4
Pre-charge Operation ..................................................4
Sleep Mode .................................................................4
Software Write Protect ................................................5
Software Write-Protect Timing ....................................7
SRAM Drop-In Replacement .......................................8
Endurance ...................................................................8
Maximum Ratings .............................................................9
Operating Range ...............................................................9
DC Electrical Characteristics ..........................................9
Data Retention and Endurance .....................................10
Capacitance ....................................................................10
Thermal Resistance ........................................................10
AC Test Conditions ........................................................10
AC Switching Characteristics .......................................11
SRAM Read Cycle ....................................................11
SRAM Write Cycle .....................................................12
Power Cycle and Sleep Mode Timing ...........................16
Functional Truth Table ...................................................17
Byte Select Truth Table ..................................................17
Ordering Information ......................................................18
Ordering Code Definitions .........................................18
Package Diagram ............................................................19
Acronyms ........................................................................20
Document Conventions .................................................20
Units of Measure .......................................................20
Document History Page .................................................21
Sales, Solutions, and Legal Information ......................22
Worldwide Sales and Design Support ....................... 22
Products ....................................................................22
PSoC® Solutions ......................................................22
Cypress Developer Community .................................22
Technical Support .....................................................22
FM28V202A
Document Number: 001-90309 Rev. *F Page 3 of 22
Pinout
Figure 1. 44-pin TSOP II pinout
Pin Definitions
Pin Name I/O Type Description
A
0
–A
16
Input Address inputs: The 17 address lines select one of 128K words in the F-RAM array. The lowest two
address lines A
1
–A
0
may be used for page mode read and write operations.
DQ
0
–DQ
15
Input/Output Data I/O Lines: 16-bit bidirectional data bus for accessing the F-RAM array.
WE
Input Write Enable: A write cycle begins when WE is asserted. The rising edge causes the FM28V202A to
write the data on the DQ bus to the F-RAM array. The falling edge of WE
latches a new column address
for page mode write cycles.
CE
Input Chip Enable: The device is selected and a new memory access begins on the falling edge of CE. The
entire address is latched internally at this point. Subsequent changes to the A
1
–A
0
address inputs allow
page mode operation.
OE
Input Output Enable: When OE is LOW, the FM28V202A drives the data bus when the valid read data is
available. Deasserting OE
HIGH tristates the DQ pins.
UB
Input Upper Byte Select: Enables DQ
15
–DQ
8
pins during reads and writes. These pins are HI-Z if UB is HIGH.
If the user does not perform byte writes and the device is not configured as a 256K × 8, the UB
and LB
pins may be tied to ground.
LB
Input Lower Byte Select: Enables DQ
7
–DQ
0
pins during reads and writes. These pins are HI-Z if LB is HIGH.
If the user does not perform byte writes and the device is not configured as a 256 K × 8, the UB
and LB
pins may be tied to ground.
ZZ
Input Sleep: When ZZ is LOW, the device enters a low-power sleep mode for the lowest supply current
condition. ZZ
must be HIGH for a normal read/write operation. This pin must be tied to V
DD
if not used.
V
SS
Ground Ground for the device. Must be connected to the ground of the system.
V
DD
Power supply Power supply input to the device.
NC No connect No connect. This pin is not connected to the die.
V
SS
DQ
6
DQ
5
DQ
4
V
DD
A
9
DQ
3
A
10
DQ
2
DQ
1
DQ
0
LB
A
12
CE
A
3
A
2
A
1
A
0
A
16
A
15
A
14
A
13
A
11
NC
A
8
UB
OE
A
7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44-pin TSOP II
Top View
(not to scale)
WE
DQ
7
A
4
V
SS
V
DD
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
(
×
16)
ZZ
A
6
A
5
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FM28V202A-TGTR

Mfr. #:
Buy FM28V202A-TGTR
Manufacturer:
Cypress Semiconductor
Description:
F-RAM 2Mb, 60Mhz 128K x 16 FRAM
Lifecycle:
New from this manufacturer.
Delivery:
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