FM28V202A
Document Number: 001-90309 Rev. *F Page 16 of 22
Power Cycle and Sleep Mode Timing
Over the Operating Range
Parameter Description Min Max Unit
t
PU
Power-up (after V
DD
min. is reached) to first access time 1 ms
t
PD
Last write (WE HIGH) to power down time 0 ms
t
VR
[11]
V
DD
power-up ramp rate 50 µs/V
t
VF
[11]
V
DD
power-down ramp rate 100 µs/V
t
ZZH
ZZ active to DQ HI-Z time 20 ns
t
WEZZ
Last write to sleep mode entry time 0 µs
t
ZZL
ZZ active LOW time 1 µs
t
ZZEN
Sleep mode entry time (ZZ LOW to CE don’t care) 0 µs
t
ZZEX
Sleep mode exit time (ZZ HIGH to 1
st
access after wakeup) 450 µs
Figure 16. Power Cycle and Sleep Mode Timing
ZZ
V
DD
min.
V
DD
WE
t
PD
CE
DQ
R/W
Allowed
t
WEZZ
t
PU
D out
t
ZZH
D in
t
ZZEX
R/W
Allowed
t
ZZEN
R/W
Allowed
t
ZZEX
V
DD
min.
t
ZZL
t
VR
t
VF
Note
11. Slope measured at any point on the V
DD
waveform.
FM28V202A
Document Number: 001-90309 Rev. *F Page 17 of 22
Functional Truth Table
CE WE A
16-2
A
1-0
ZZ Operation
[12, 13]
X X X X L Sleep Mode
H X X X H Standby/Idle
L
H
H
V
V
V
V
H
H
Read
L H No Change Change H Page Mode Read
L H Change V H Random Read
L
L
L
V
V
V
V
H
H
CE
-Controlled Write
[13]
LVVHWE-Controlled Write
[13, 14]
L No Change V H Page Mode Write
[15]
L
X
X
X
X
X
X
H
H
Starts pre-charge
Byte Select Truth Table
WE OE LB UB Operation
[16]
H H X X Read; Outputs disabled
XHH
H L H L Read upper byte; HI-Z lower byte
L H Read lower byte; HI-Z upper byte
L L Read both bytes
L X H L Write upper byte; Mask lower byte
L H Write lower byte; Mask upper byte
L L Write both bytes
Notes
12. H = Logic HIGH, L = Logic LOW, V = Valid Data, X = Don't Care, = toggle LOW, = toggle HIGH.
13. For write cycles, data-in is latched on the rising edge of CE
or WE, whichever comes first.
14. WE
-controlled write cycle begins as a Read cycle and then A
16-2
is latched.
15. Addresses A
1-0
must remain stable for at least 15 ns during page mode operation.
16. The UB
and LB pins may be grounded if 1) the system does not perform byte writes and 2) the device is not configured as a 256K x 8.
FM28V202A
Document Number: 001-90309 Rev. *F Page 18 of 22
Ordering Code Definitions
Ordering Information
Access
time
(ns)
Ordering Code
Package
Diagram
Package Type
Operating
Range
60 FM28V202A-TG 51-85087 44-pin TSOP II with software WP, sleep mode Industrial
FM28V202A-TGTR
All the above parts are Pb-free.
Option:
blank = Standard; TR = Tape and Reel
Package Type:
TG = 44-pin TSOP II
Die Revision: A
Density: 202 = 2-Mbit
Voltage: V = 2.0 V to 3.6 V
Parallel F-RAM
Cypress
28FM V 202 A - TG TR

FM28V202A-TGTR

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
F-RAM 2Mb, 60Mhz 128K x 16 FRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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