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FM28V202A-TGTR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
FM28V202A
Document Number: 001-90309 Rev. *F Page 13 of 22
Figure 8. Read Cycle Timing 1 (CE
LOW, OE LOW)
Figure 9. Read Cycle Timing 2 (CE
Controlled)
Figure 10. Page Mode Read Cycle Timing
[8]
t
AA
Previous Data
Valid Data
t
OH
Valid Data
t
AA
t
OH
DQ
15-0
A
t
RC
t
RC
16-2
t
AS
A
DQ
t
CE
t
HZ
t
OE
t
OH
t
OHZ
UB / LB
OE
CE
t
BA
t
BHZ
t
CA
t
PC
t
AH
16-0
15-0
t
AS
t
HZ
t
AAP
t
OHP
CE
A
OE
DQ
t
CA
A
t
OE
t
CE
t
OHZ
t
PC
Data 0 Data 1 Data 2
Col 0 Col 1 Col 2
16-2
1-0
15-0
Note
8. Although sequential column addressing is shown, it is not required
FM28V202A
Document Number: 001-90309 Rev. *F Page 14 of 22
Figure 11. Write Cycle Timing 1 (WE Controlled)
[9]
Figure 12. Write Cycle Timing 2 (CE Controlled)
Figure 13. Write Cycle Timing 3 (CE
LOW)
[9]
t
WZ
t
HZ
D in
CE
A
WE
t
CA
t
PC
DQ
t
WP
t
CW
t
AS
D out
D out
t
DS
t
DH
t
WLC
15-0
16-0
t
WX
CE
A
WE
DQ
t
AS
t
DH
t
DS
D in
t
CA
t
PC
UB/LB
t
BLC
15-0
16-0
t
DH
t
WX
D out D in
A
WE
DQ
t
WC
t
WLA
t
DS
t
AWH
D out
t
WZ
D in
16-0
15-0
Note
9. OE
(not shown) is LOW only to show the effect of WE on DQ pins.
FM28V202A
Document Number: 001-90309 Rev. *F Page 15 of 22
Figure 14. Write Cycle Timing 4 (CE LOW)
[10]
Figure 15. Page Mode Write Cycle Timing
t
BDS
t
DH
D in
A
WE
DQ
t
WP3
D in
UB/LB
t
WP2
t
DS
t
DH
t
DS
t
BDH
15-0
16-0
t
ASP
t
DH
CE
A
WE
t
CA
t
PC
t
CW
Col 0 Col 1
Data 0
Col 2
t
AS
t
DS
Data 1
t
WP
Data 2
OE
t
AHP
t
PWC
t
WLC
16-2
A
1-0
DQ
15-0
Note
10. UB
and LB to show byte enable and byte masking cases.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

FM28V202A-TGTR

Mfr. #:
Buy FM28V202A-TGTR
Manufacturer:
Cypress Semiconductor
Description:
F-RAM 2Mb, 60Mhz 128K x 16 FRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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