Document Number: 001-90309 Rev. *F Page 4 of 22
Device Operation
The FM28V202A is a word wide F-RAM memory logically
organized as 131,072 × 16 and accessed using an
industry-standard parallel interface. All data written to the part is
immediately nonvolatile with no delay. The device offers page
mode operation, which provides high-speed access to
addresses within a page (row). Access to a different page
requires that either CE
transitions LOW or the upper address
(A
16
–A
2
) changes. See the Functional Truth Table on page 17
for a complete description of read and write modes.
Memory Operation
Users access 131,072 memory locations, each with 16 data bits
through a parallel interface. The F-RAM array is organized as
eight blocks, each having 4096 rows. Each row has four column
locations, which allow fast access in page mode operation.
When an initial address is latched by the falling edge of CE
,
subsequent column locations may be accessed without the need
to toggle CE
. When CE is deasserted HIGH, a pre-charge
operation begins. Writes occur immediately at the end of the
access with no delay. The WE pin must be toggled for each write
operation. The write data is stored in the nonvolatile memory
array immediately, which is a feature unique to F-RAM called
NoDelay writes.
Read Operation
A read operation begins on the falling edge of CE. The falling
edge of CE causes the address to be latched and starts a
memory read cycle if WE is HIGH. Data becomes available on
the bus after the access time is met. When the address is latched
and the access completed, a new access to a random location
(different row) may begin while CE
is still LOW. The minimum
cycle time for random addresses is t
RC
. Note that unlike SRAMs,
the FM28V202A's CE-initiated access time is faster than the
address access time.
The FM28V202A will drive the data bus when OE
and at least
one of the byte enables (UB
, LB) is asserted LOW. The upper
data byte is driven when UB
is LOW, and the lower data byte is
driven when LB is LOW. If OE is asserted after the memory
access time is met, the data bus will be driven with valid data. If
OE
is asserted before completing the memory access, the data
bus will not be driven until valid data is available. This feature
minimizes supply current in the system by eliminating transients
caused by invalid data being driven to the bus. When OE
is
deasserted HIGH, the data bus will remain in a HI-Z state.
Write Operation
In the FM28V202A, writes occur in the same interval as reads.
The FM28V202A supports both CE
and WE controlled write
cycles. In both cases, the address A
16
–A
2
is latched on the
falling edge of CE
.
In a CE
-controlled write, the WE signal is asserted before
beginning the memory cycle. That is, WE
is LOW when CE falls.
In this case, the device begins the memory cycle as a write. The
FM28V202A will not drive the data bus regardless of the state of
OE
as long as WE is LOW. Input data must be valid when CE is
deasserted HIGH. In a WE
-controlled write, the memory cycle
begins on the falling edge of CE. The WE signal falls some time
later. Therefore, the memory cycle begins as a read. The data
bus will be driven if OE
is LOW; however, it will be HI-Z when WE
is asserted LOW. The CE- and WE-controlled write timing cases
are shown in the Switching Waveforms on page 13.
Write access to the array begins on the falling edge of WE
after
the memory cycle is initiated. The write access terminates on the
rising edge of WE
or CE, whichever comes first. A valid write
operation requires the user to meet the access time specification
before deasserting WE
or CE. The data setup time indicates the
interval during which data cannot change before the end of the
write access (rising edge of WE or CE).
Unlike other nonvolatile memory technologies, there is no write
delay with F-RAM. Because the read and write access times of
the underlying memory are the same, the user experiences no
delay through the bus. The entire memory operation occurs in a
single bus cycle. Data polling, a technique used with EEPROMs
to determine if a write is complete, is unnecessary.
Page Mode Operation
The F-RAM array is organized as eight blocks, each having 4096
rows. Each row has four column-address locations. Address
inputs A
1
–A
0
define the column address to be accessed. An
access can start on any column address, and other column
locations may be accessed without the need to toggle the CE pin.
For fast access reads, after the first data byte is driven to the bus,
the column address inputs A
1
–A
0
may be changed to a new
value. A new data byte is then driven to the DQ pins no later than
t
AAP
, which is less than half the initial read access time. For fast
access writes, the first write pulse defines the first write access.
While CE is LOW, a subsequent write pulse along with a new
column address provides a page mode write access.
Pre-charge Operation
The pre-charge operation is an internal condition in which the
memory state is prepared for a new access. Pre-charge is
user-initiated by driving the CE
signal HIGH. It must remain
HIGH for at least the minimum pre-charge time, t
PC
.
Pre-charge is also activated by changing the upper addresses,
A
16
–A
2
. The current row is first closed before accessing the new
row. The device automatically detects an upper order address
change, which starts a pre-charge operation. The new address
is latched and the new read data is valid within the t
AA
address
access time; see Figure 8 on page 13. A similar sequence occurs
for write cycles; see Figure 13 on page 14. The rate at which
random addresses can be issued is t
RC
and t
WC
, respectively.
Sleep Mode
The device incorporates a sleep mode of operation, which allows
the user to achieve the lowest power supply current condition. It
enters a low-power sleep mode by asserting the ZZ pin LOW.
Read and write operations must complete before the ZZ
pin
going LOW. When ZZ
is LOW, all pins are ignored except the ZZ
pin. When ZZ is deasserted HIGH, there is some time delay
(t
ZZEX
) before the user can access the device. If sleep mode is
not used, the ZZ
pin must be tied to V
DD
.
