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89H32T8G2ZCBLGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
10 of 39 November 28, 2011
IDT 89HPES32T8G2 Data Sheet
Pin Characteristics
Note: Some input pads of the switch do not contain internal pull-ups or pull-downs. Unused SMBus and System inputs should be tied off to
appropriate levels. This is especially critical for unused control signal inputs which, if left floating, could adversely affect operation. Also, floating
pins can cause a slight increase in power consumption. Unused Serdes (Rx and Tx) pins should be left floating. Finally, No Connection pins
should not be connected.
Function Pin Name Type Buffer
I/O
Type
Internal
Resistor
1
Notes
PCI Express Interface PE00RN[3:0] I PCIe
differential
2
Serial Link
PE00RP[3:0] I
PE00TN[3:0] O
PE00TP[3:0] O
PE01RN[3:0] I
PE01RP[3:0] I
PE01TN[3:0] O
PE01TP[3:0] O
PE02RN[3:0] I
PE02RP[3:0] I
PE02TN[3:0] O
PE02TP[3:0] O
PE03RN[3:0] I
PE03RP[3:0] I
PE03TN[3:0] O
PE03TP[3:0] O
PE04RN[3:0] I
PE04RP[3:0] I
PE04TN[3:0] O
PE04TP[3:0] O
PE05RN[3:0] I
PE05RP[3:0] I
PE05TN[3:0] O
PE05TP[3:0] O
PE06RN[3:0] I
PE06RP[3:0] I
PE06TN[3:0] O
PE06TP[3:0] O
PE07RN[3:0] I
PE07RP[3:0] I
PE07TN[3:0] O
PE07TP[3:0] O
GCLKN[1:0] I HCSL Diff. Clock
Input
Refer to Table 9
GCLKP[1:0] I
Table 8 Pin Characteristics (Part 1 of 2)
11 of 39 November 28, 2011
IDT 89HPES32T8G2 Data Sheet
SMBus MSMBCLK I/O LVTTL STI
3
pull-up on board
MSMBDAT I/O STI pull-up on board
SSMBADDR[2,1] I Input pull-up
SSMBCLK I/O STI pull-up on board
SSMBDAT I/O STI pull-up on board
General Purpose I/O GPIO[8:0] I/O LVTTL STI,
High Drive
pull-up
System Pins CLKMODE[1:0] I LVTTL Input pull-up
GCLKFSEL I pull-down
P01MERGEN I pull-down
P23MERGEN I pull-down
P45MERGEN I pull-down
P67MERGEN I pull-down
PERSTN I STI
RSTHALT I Input pull-down
SWMODE[3:0] I pull-down
EJTAG / JTAG JTAG_TCK I LVTTL STI pull-up
JTAG_TDI I STI pull-up
JTAG_TDO O
JTAG_TMS I STI pull-up
JTAG_TRST_N I STI pull-up
SerDes Reference
Resistors
REFRES00 I/O Analog
REFRES01 I/O
REFRES02 I/O
REFRES03 I/O
REFRES04 I/O
REFRES05 I/O
REFRES06 I/O
REFRES07 I/O
REFRESPLL I/O
1.
Internal resistor values under typical operating conditions are 92K Ω for pull-up and 91K Ω for pull-down.
2.
All receiver pins set the DC common mode voltage to ground. All transmitters must be AC coupled to the media.
3.
Schmitt Trigger Input (STI).
Function Pin Name Type Buffer
I/O
Type
Internal
Resistor
1
Notes
Table 8 Pin Characteristics (Part 2 of 2)
12 of 39 November 28, 2011
IDT 89HPES32T8G2 Data Sheet
Logic Diagram — PES32T8G2
Figure 3 PES32T8G2 Logic Diagram
PE00TP[3:0]
Global
Reference Clocks
GCLKN[1:0]
GCLKP[1:0]
JTAG_TCK
GPIO[8:0]
9
General Purpose
I/O
V
DD
CORE
V
DD
I/O
V
DD
PEA
Power/Ground
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
Master
SMBus Interface
Slave
SMBus Interface
GCLKFSEL
RSTHALT
System
Pins
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
JTAG Pins
V
SS
SWMODE[3:0]
4
CLKMODE[1:0]
PERSTN
PE00RP[3:0]
PE00RN[3:0]
PCI Express
Switch
SerDes Input
PE00TN[3:0]
PCI Express
Switch
SerDes Output
Port 0
Port 0
PE07RP[3:0]
PE07RN[3:0]
PCI Express
Switch
SerDes Input
PE07TP[3:0]
PE07TN[3:0]
PCI Express
Switch
SerDes Output
Port 7
Port 7
PES32T8G2
REFRES[7:0]
SerDes
Reference
Resistors
V
DD
PEHA
V
DD
PETA
......
2
P01MERGEN
P23MERGEN
PE01TP[3:0]
PE01TN[3:0]
PCI Express
Switch
SerDes Output
Port 1
PE01RP[3:0]
PE01RN[3:0]
PCI Express
Switch
SerDes Input
Port 1
......
PE02RP[3:0]
PE02RN[3:0]
PCI Express
Switch
SerDes Input
Port 2
PE02TP[3:0]
PE02TN[3:0]
PCI Express
Switch
SerDes Output
Port 2
SSMBADDR[2,1]
REFRESPLL
P45MERGEN
P67MERGEN
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

89H32T8G2ZCBLGI

Mfr. #:
Buy 89H32T8G2ZCBLGI
Manufacturer:
IDT
Description:
PCI Interface IC PCIE GEN2 SWITCH
Lifecycle:
New from this manufacturer.
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