89H32T8G2ZCBLGI Datasheet 89H32T8G2ZCBLGI, 89H32T8G2ZCBLG8, 89H32T8G2ZCBLGI8 | P4-P6

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IDT 89HPES32T8G2 Data Sheet

Hot-Plug Interface

The PES32T8G2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES32T8G2

utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configura-

tion, whenever the state of a Hot-Plug output needs to be modified, the PES32T8G2 generates an SMBus transaction to the I/O expander with the

new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN

input pin (alternate function of GPIO) of the PES32T8G2. In response to an I/O expander interrupt, the PES32T8G2 generates an SMBus transaction

to read the state of all of the Hot-Plug inputs from the I/O expander.

General Purpose Input/Output

The PES32T8G2 provides 9 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin

may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These

alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.

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IDT 89HPES32T8G2 Data Sheet

Pin Description

The following tables list the functions of the pins provided on the PES32T8G2. Some of the functions listed may be multiplexed onto the same pin.

The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)

level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.

Signal Type Name/Description

PE00RP[3:0]

PE00RN[3:0]

I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive

pairs for port 0.

PE00TP[3:0]

PE00TN[3:0]

O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 0.

PE01RP[3:0]

PE01RN[3:0]

I PCI Express Port 1 Serial Data Receive. Differential PCI Express receive

pairs for port 1. When port 0 is merged with port 1, these signals become

port 0 receive pairs for lanes 4 through 7.

PE01TP[3:0]

PE01TN[3:0]

O PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 1. When port 0 is merged with port 1, these signals

become port 0 transmit pairs for lanes 4 through 7.

PE02RP[3:0]

PE02RN[3:0]

I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive

pairs for port 2.

PE02TP[3:0]

PE02TN[3:0]

O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 2.

PE03RP[3:0]

PE03RN[3:0]

I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive

pairs for port 3. When port 2 is merged with port 3, these signals become

port 2 receive pairs for lanes 4 through 7.

PE03TP[3:0]

PE03TN[3:0]

O PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 3. When port 2 is merged with port 3, these signals

become port 2 transmit pairs for lanes 4 through 7.

PE04RP[3:0]

PE04RN[3:0]

I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive

pairs for port 4.

PE04TP[3:0]

PE04TN[3:0]

O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 4.

PE05RP[3:0]

PE05RN[3:0]

I PCI Express Port 5 Serial Data Receive. Differential PCI Express receive

pairs for port 5. When port 4 is merged with port 5, these signals become

port 4 receive pairs for lanes 4 through 7.

PE05TP[3:0]

PE05TN[3:0]

O PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 5. When port 4 is merged with port 5, these signals

become port 4 transmit pairs for lanes 4 through 7.

PE06RP[3:0]

PE06RN[3:0]

I PCI Express Port 6 Serial Data Receive. Differential PCI Express receive

pairs for port 6.

PE06TP[3:0]

PE06TN[3:0]

O PCI Express Port 6 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 6.

PE07RP[3:0]

PE07RN[3:0]

I PCI Express Port 7 Serial Data Receive. Differential PCI Express receive

pairs for port 7. When port 6 is merged with port 7, these signals become

port 6 receive pairs for lanes 4 through 7.

PE07TP[3:0]

PE07TN[3:0]

O PCI Express Port 7 Serial Data Transmit. Differential PCI Express trans-

mit pairs for port 7. When port 6 is merged with port 7, these signals

become port 6 transmit pairs for lanes 4 through 7.

Table 1 PCI Express Interface Pins

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IDT 89HPES32T8G2 Data Sheet

Signal Type Name/Description

GCLKN[1:0]

GCLKP[1:0]

I Global Reference Clock. Differential reference clock input pair. This clock

is used as the reference clock by on-chip PLLs to generate the clocks

required for the system logic. The frequency of the differential reference

clock is determined by the GCLKFSEL signal.

Table 2 Reference Clock Pins

Signal Type Name/Description

MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize

transfers on the master SMBus.

MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the mas-

ter SMBus.

SSMBADDR[2,1] I Slave SMBus Address. These pins determine the SMBus address to

which the slave SMBus interface responds.

SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize trans-

fers on the slave SMBus.

SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave

SMBus.

Table 3 SMBus Interface Pins

Signal Type Name/Description

GPIO[0] I/O General Purpose I/O.