16 of 39 November 28, 2011
IDT 89HPES32T8G2 Data Sheet
Recommended Operating Supply Voltages
Power-Up/Power-Down Sequence
During power supply ramp-up, V
DD
CORE must remain at least 1.0V below V
DD
I/O at all times. There are no other power-up sequence require-
ments for the various operating supply voltages.
The power-down sequence can occur in any order.
Recommended Operating Temperature
Symbol Parameter Minimum Typical Maximum Unit
V
DD
CORE Internal logic supply 0.9 1.0 1.1 V
V
DD
I/O I/O supply except for SerDes 2.25 2.5 2.75 V
3.125 3.3 3.465 V
V
DD
PEA
1
1.
V
DD
PEA and V
DD
PETA should have no more than 25mV
peak-peak
AC power supply noise superimposed on the 1.0V nominal DC value.
PCI Express Analog Power 0.95 1.0 1.1 V
V
DD
PEHA
2
2.
V
DD
PEHA should have no more than 50mV
peak-peak
AC power supply noise superimposed on the 2.5V nominal DC value.
PCI Express Analog High Power 2.25 2.5 2.75 V
V
DD
PETA
1
PCI Express Transmitter Analog Voltage 0.95 1.0 1.1 V
V
SS
Common ground 0 0 0 V
Table 13 PES32T8G2 Operating Voltages
Grade Temperature
Commercial 0
°C to +70°C Ambient
Industrial -40°C to +85°C Ambient
Table 14 PES32T8G2 Operating Temperatures
17 of 39 November 28, 2011
IDT 89HPES32T8G2 Data Sheet
Power Consumption
Typical power is measured under the following conditions: 25°C Ambient, 35% total link usage on all ports, typical voltages defined in Table 13
(and also listed below).
Maximum power is measured under the following conditions: 70°C Ambient, 85% total link usage on all ports, maximum voltages defined in
Table 13 (and also listed below).
Note 1: I/O supply of 3.3V is preferred.
Note 2: The above power consumption assumes that all ports are functioning at Gen2 (5.0 GT/S) speeds. Power consumption can be
reduced by turning off unused ports through software or through boot EEPROM. Power savings will occur in V
DD
PEA, V
DD
PEHA, and
V
DD
PETA. Power savings can be estimated as directly proportional to the number of unused ports, since the power consumption of a turned-
off port is close to zero. For example, if 2 ports out of 8 are turned off, then the power savings for each of the above three power rails can be
calculated quite simply as 2/8 multiplied by the power consumption indicated in the above table.
Note 3: Using a port in Gen1 mode (2.5GT/S) results in approximately 18% power savings for each power rail: V
DD
PEA, V
DD
PEHA, and
V
DD
PETA.
Number of Active
Lanes per Port
Core Supply
PCIe Analog
Supply
PCIe Analog
High Supply
PCIe
Transmitter
Supply
I/O Supply Total
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
Power
Max
Power
8/8/8/8
(Full Swing)
mA 2850 5000 1514 1826 507 514 561 603 24 29
Watts 2.85 5.50 1.51 2.01 1.27 1.41 0.56 0.66 0.06 0.08 6.25 9.67
8/8/8/8
(Half Swing)
mA 2850 5000 1302 1571 507 514 292 313 24 29
Watts 2.85 5.50 1.30 1.73 1.27 1.41 0.29 0.34 0.06 0.08 5.77 9.07
Table 15 PES32T8G2 Power Consumption — 2.5V I/O
Number of Active
Lanes per Port
Core Supply
PCIe Analog
Supply
PCIe Analog
High Supply
PCIe
Transmitter
Supply
I/O Supply Total
Typ
1.0V
Max
1.1V
Typ
1.0V
Max
1.1V
Typ
2.5V
Max
2.75V
Typ
1.0V
Max
1.1V
Typ
3.3V
Max
3.465V
Typ
Power
Max
Power
8/8/8/8
(Full Swing)
mA 2850 5000 1514 1826 507 514 561 603 30 35
Watts 2.85 5.50 1.51 2.01 1.27 1.41 0.56 0.66 0.10 0.12 6.29 9.71
8/8/8/8
(Half Swing)
mA 2850 5000 1302 1571 507 514 292 313 30 35
Watts 2.85 5.50 1.30 1.73 1.27 1.41 0.29 0.34 0.10 0.12 5.81 9.11
Table 16 PES32T8G2 Power Consumption — 3.3V I/O
18 of 39 November 28, 2011
IDT 89HPES32T8G2 Data Sheet
Thermal Considerations
This section describes thermal considerations for the PES32T8G2 (23mm
2
FCBGA484 package). The data in Table 17 below contains information
that is relevant to the thermal performance of the PES32T8G2 switch.
Note: It is important for the reliability of this device in any user environment that the junction temperature not exceed the T
J(max)
value
specified in Table 17. Consequently, the effective junction to ambient thermal resistance (
θ
JA
) for the worst case scenario must be
maintained below the value determined by the formula:
θ
JA
= (T
J(max)
- T
A(max)
)/P
Given that the values of T
J(max)
, T
A(max)
, and P are known, the value of desired θ
JA
becomes a known entity to the system designer. How to
achieve the desired
θ
JA
is left up to the board or system designer, but in general, it can be achieved by adding the effects of θ
JC
(value
provided in Table 17), thermal resistance of the chosen adhesive (
θ
CS
), that of the heat sink (θ
SA
), amount of airflow, and properties of the
circuit board (number of layers and size of the board). It is strongly recommended that users perform their own thermal analysis for their own
board and system design scenarios.
Symbol Parameter Value Units Conditions
T
J(max)
Junction Temperature 125
o
C Maximum
T
A(max)
Ambient Temperature 70
o
C Maximum for commercial-rated products
85
o
C Maximum for industrial-rated products
θ
JA(effective)
Effective Thermal Resistance, Junction-to-Ambient
15.2
o
C/W Zero air flow
8.5
o
C/W 1 m/S air flow
7.1
o
C/W 2 m/S air flow
θ
JB
Thermal Resistance, Junction-to-Board 3.1
o
C/W
θ
JC
Thermal Resistance, Junction-to-Case 0.15
o
C/W
P Power Dissipation of the Device 9.71 Watts Maximum
Table 17 Thermal Specifications for PES32T8G2, 23x23 mm FCBGA484 Package

89H32T8G2ZCBLGI

Mfr. #:
Manufacturer:
IDT
Description:
PCI Interface IC PCIE GEN2 SWITCH
Lifecycle:
New from this manufacturer.
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