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89H32T8G2ZCBLGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39
7 of 39 November 28, 2011
IDT 89HPES32T8G2 Data Sheet
GPIO[6] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[7] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[8] I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN
Alternate function pin type: Input
Alternate function: IO expander interrupt.
Signal Type Name/Description
CLKMODE[1:0] Clock Mode. These signals determine the port clocking mode used by
ports of the device.
GCLKFSEL I Global Clock Frequency Select. These signals select the frequency of
the GCLKP and GCLKN signals.
0x0 100 MHz
0x1 125 MHz
P01MERGEN I Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low
internally. When this pin is low, port 0 is merged with port 1 to form a single
x8 port. The Serdes lanes associated with port 1 become lanes 4 through 7
of port 0. When this pin is high, port 0 and port 1 are not merged, and each
operates as a single x4 port.
P23MERGEN I Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled low
internally. When this pin is low, port 2 is merged with port 3 to form a single
x8 port. The Serdes lanes associated with port 3 become lanes 4 through 7
of port 2. When this pin is high, port 2 and port 3 are not merged, and each
operates as a single x4 port.
P45MERGEN I Port 4 and 5 Merge. P45MERGEN is an active low signal. It is pulled low
internally. When this pin is low, port 4 is merged with port 5 to form a single
x8 port. The Serdes lanes associated with port 5 become lanes 4 through 7
of port 4. When this pin is high, port 4 and port 5 are not merged, and each
operates as a single x4 port.
P67MERGEN I Port 6 and 7 Merge. P67MERGEN is an active low signal. It is pulled low
internally. When this pin is low, port 6 is merged with port 7 to form a single
x8 port. The Serdes lanes associated with port 7 become lanes 4 through 7
of port 6. When this pin is high, port 6 and port 7 are not merged, and each
operates as a single x4 port.
Table 5 System Pins (Part 1 of 2)
Signal Type Name/Description
Table 4 General Purpose I/O Pins (Part 2 of 2)
8 of 39 November 28, 2011
IDT 89HPES32T8G2 Data Sheet
PERSTN I Global Reset. Assertion of this signal resets all logic inside PES32T8G2.
RSTHALT I Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, PES32T8G2 executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the SWCTL register by an SMBus master.
SWMODE[3:0] I Switch Mode. These configuration pins determine the PES32T8G2 switch
operating mode. Note: These pins should be static and not change follow-
ing the negation of PERSTN.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - Single partition with port 0 selected as the upstream port (port 2 dis-
abled)
0x9 - Single partition with port 2 selected as the upstream port (port 0 dis-
abled)
0xA - Single partition with Serial EEPROM initialization and port 0 selected
as the upstream port (port 2 disabled)
0xB - Single partition with Serial EEPROM initialization and port 2 selected
as the upstream port (port 0 disabled)
0xE - Reserved
0xF - Reserved
Signal Type Name/Description
JTAG_TCK I JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG_TDI I JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
JTAG_TDO O JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG_TMS I JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG_TRST_N I JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins
Signal Type Name/Description
Table 5 System Pins (Part 2 of 2)
9 of 39 November 28, 2011
IDT 89HPES32T8G2 Data Sheet
Signal Type Name/Description
REFRES00 I/O Port 0 External Reference Resistor. Provides a reference for the Port 0
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
REFRES01 I/O Port 1 External Reference Resistor. Provides a reference for the Port 1
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
REFRES02 I/O Port 2 External Reference Resistor. Provides a reference for the Port 2
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
REFRES03 I/O Port 3 External Reference Resistor. Provides a reference for the Port 3
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
REFRES04 I/O Port 4 External Reference Resistor. Provides a reference for the Port 4
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
REFRES05 I/O Port 5 External Reference Resistor. Provides a reference for the Port 5
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
REFRES06 I/O Port 6 External Reference Resistor. Provides a reference for the Port 6
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
REFRES07 I/O Port 7 External Reference Resistor. Provides a reference for the Port 7
SerDes bias currents and PLL calibration circuitry. A 3 kOhm +/- 1% resis-
tor should be connected from this pin to ground.
REFRESPLL I/O PLL External Reference Resistor. Provides a reference for the PLL bias
currents and PLL calibration circuitry. A 3K Ohm +/- 1% resistor should be
connected from this pin to ground.
V
DD
CORE I Core V
DD.
Power supply for core logic (1.0V).
V
DD
I/O I I/O V
DD.
LVTTL I/O buffer power supply (2.5V or preferred 3.3V).
V
DD
PEA I PCI Express Analog Power. Serdes analog power supply (1.0V).
V
DD
PEHA I PCI Express Analog High Power. Serdes analog power supply (2.5V).
V
DD
PETA I PCI Express Transmitter Analog Voltage. Serdes transmitter analog
power supply (1.0V).
V
SS
I Ground.
Table 7 Power, Ground, and SerDes Resistor Pins
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39

89H32T8G2ZCBLGI

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Buy 89H32T8G2ZCBLGI
Manufacturer:
IDT
Description:
PCI Interface IC PCIE GEN2 SWITCH
Lifecycle:
New from this manufacturer.
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