5P49V5901B045NLGI8 Datasheet 5P49V5901B000NLGI8, 5P49V5901B558NLGI8, 5P49V5901B034NLGI8 | P10-P12

PROGRAMMABLE CLOCK GENERATOR 10 MARCH 3, 2017

5P49V5901 DATASHEET

C Mode Operation

The device acts as a slave device on the I

C bus using one of

the two I

C addresses (0xD0 or 0xD4) to allow multiple

devices to be used in the system. The interface accepts

byte-oriented block write and block read operations. Two

address bytes specify the register address of the byte position

of the first register to write or read. Data bytes (registers) are

accessed in sequential order from the lowest to the highest

byte (most significant bit first). Read and write block transfers

can be stopped after any complete byte transfer. During a

write operation, data will not be moved into the registers until

the STOP bit is received, at which point, all data received in

the block write will be written simultaneously.

For full electrical I

C compliance, it is recommended to use

external pull-up resistors for SDATA and SCLK. The internal

pull-down resistors have a size of 100k typical.

C Slave Read and Write Cycle Sequencing

CurrentRead

S DevAd dr+R A Data0 A Data1 A A Datan Abar P

SequentialRead

S DevAddr+W A

Data0 A Data1 A A Datan Abar P

RegstartAddr A

Sr DevAddr+R A

SequentialWrite

S DevAddr+W A

Data0 PA Data1 A A Datan A

frommastertoslave

fromslavetomaster

RegstartAddr A

S=start

Sr=repeatedstart

A=acknowledge

Abar=noneacknowledge

P=stop

MARCH 3, 2017 11 PROGRAMMABLE CLOCK GENERATOR

5P49V5901 DATASHEET

Table 6:I

C Bus DC Characteristics

Table 7:I

C Bus AC Characteristics

Symbol Parameter Conditions Min Typ Max Unit

VIH Input HIGH Level

For SEL1/SDA pin and SEL0/SCL pi

0.7xVDDD 5.5

VIL Input LOW Level

For SEL1/SDA pin and SEL0/SCL pi

GND-0.3 0.3xVDDD V

VHYS Hysteresis of Inputs 0.05xVDDD V

IIN Input Leakage Current -1 30 µA

VOL Output LOW Voltage IOL = 3 mA 0.4 V

Symbol Parameter Min Typ Max Unit

FSCLK Serial Clock Frequency (SCL) 10 400 kHz

tBUF Bus free time between STOP and START 1.3 µs

tSU:START Setup Time, START 0.6 µs

tHD:START Hold Time, START 0.6 µs

tSU:DATA Setup Time, data input (SDA) 0.1 µs

tHD:DATA Hold Time, data input (SDA) 1 0 µs

tOVD Output data valid from clock 0.9 µs

CB Capacitive Load for Each Bus Line 400 pF

tR Rise Time, data and clock (SDA, SCL) 20 + 0.1xCB 300 ns

tF Fall Time, data and clock (SDA, SCL) 20 + 0.1xCB 300 ns

tHIGH HIGH Time, clock (SCL) 0.6 µs

tLOW LOW Time, clock (SCL) 1.3 µs

tSU:STOP Setup Time, STOP 0.6 µs

Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the

undefined region of the falling edge of SCL.

Note 2: I2C inputs are 5V tolerant.

PROGRAMMABLE CLOCK GENERATOR 12 MARCH 3, 2017

5P49V5901 DATASHEET

Table 8:Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the 5P49V5901. These ratings, which are standard values for IDT

commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect

product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.

Table 9:Recommended Operation Conditions

Note: V

DDO

1, V

DDO

2, V

DDO

3, and V

DDO

4 must be powered on either before or simultaneously with V

DDD

, V

DDA

and V

DDO

Item Rating

Supply Voltage, V

DDA,

DDD,

DDO

3.465V

Inputs

XIN/REF

CLKIN, CLKINB

Other inputs

0V to 1.2V voltage swing

0V to 1.2V voltage swing single-ended

-0.5V to V

DDD

Outputs, V

DDO

(LVCMOS) -0.5V to V

DDO

+ 0.5V

Outputs, I

(SDA) 10mA

Package Thermal Impedance, 

42C/W (0 mps)

Package Thermal Impedance, 

41.8C/W (0 mps)

Storage Temperature, T

STG

-65C to 150C

ESD Human Body Model 2000V

Junction Temperature 125°C

Symbol Parameter Min Typ Max Unit

DDOX

Power supply voltage for supporting 1.8V outputs

1.71 1.8 1.89 V

DDOX

Power supply voltage for supporting 2.5V outputs

2.375 2.5 2.625 V

DDOX

Power supply voltage for supporting 3.3V outputs

3.135 3.3 3.465 V

DDD

Power supply voltage for core logic functions

1.71 3.465 V

DDA

Analog power supply voltage. Use filtered analog power

supply.

1.71 3.465 V

Operating temperature, ambient

-40 +85 °C

LOAD_OUT

Maximum load capacitance (3.3V LVCMOS only)

15 pF

External reference crystal

840MHz

External reference clock CLKIN, CLKINB

5350

Power up time for all V

s to reach minimum specified

voltage (power ramps must be monotonic)

0.05 5 ms

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P37

5P49V5901B045NLGI8

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Manufacturer:

IDT

Description:

Clock Generators & Support Products VersaClock 5 CLK Gen 350MHz 2 Input

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5P49V5901B045NLGI8

5P49V5901B045NLGI8

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