AD7492
Rev. A | Page 12 of 24
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a point
1/2 LSB below the first code transition, and full scale, a point
1/2 LSB above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, that is, AGND + 1 LSB.
Gain Error
The last transition should occur at the analog value 1 1/2 LSB
below the nominal full scale. The first transition is a 1/2 LSB
above the low end of the scale (zero in the case of AD7492). The
gain error is the deviation of the actual difference between the
first and last code transitions from the ideal difference between
the first and last code transitions with offset errors removed.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode after the end
of the conversion. Track/Hold acquisition time is the time
required for the output of the track/hold amplifier to reach its
final value, within ±0.5 LSB, after the end of conversion.
Signal-to-Noise and Distortion Ratio
This is the measured ratio of signal-to-noise and distortion at
the output of the A/D converter. The signal is the rms
amplitude of the fundamental. Noise is the sum of all
nonfundamental signals up to half the sampling frequency
(f
S
/2), excluding dc. The ratio is dependent on the number of
quantization levels in the digitization process; the more levels,
the smaller the quantization noise. The theoretical signal to
(noise + distortion) ratio for an ideal N-bit converter with a sine
wave input is given by:
Signal-to-Noise and Distortion = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB and for a 10-bit
converter is 62 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7492 it is defined as:
(
)
1
2
6
2
5
2
4
2
3
2
2
log20)(
V
VVVVV
dBTHD
++++
=
where:
V
1
is the rms amplitude of the fundamental.
V
2
, V
3
, V
4
, V
5
, and V
6
are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to f
S
/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those
for which neither m nor n is equal to zero. For example, the
second order terms include (fa + fb) and (fa − fb), while the
third order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and
(fa − 2fb).
The AD7492 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second order terms are usually distanced in
frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dBs.
Aperture Delay
In a sample/hold, the time required after the hold command for
the switch to open fully is the aperture delay. The sample is, in
effect, delayed by this interval, and the hold command would
have to be advanced by this amount for precise timing.
Aperture Jitter
Aperture jitter is the range of variation in the aperture delay. In
other words, it is the uncertainty about when the sample is
taken. Jitter is the result of noise that modulates the phase of the
hold command. This specification establishes the ultimate
timing error, hence the maximum sampling frequency for a
given resolution. This error increases as the input dV/dt
increases.
AD7492
Rev. A | Page 13 of 24
CIRCUIT DESCRIPTION
CONVERTER OPERATION
The AD7492 is a 12-bit successive approximation analog-to-
digital converter based around a capacitive DAC. The AD7492
can convert analog input signals in the range 0 V to V
REF
. Figure
12
shows a very simplified schematic of the ADC. The control
logic, SAR register, and capacitive DAC are used to add and
subtract fixed amounts of charge from the sampling capacitor to
bring the comparator back into a balanced condition.
SWITCHES
SAR
CONTROL LOGIC
COMPARATO
R
V
REF
V
IN
C
ONTROL
INPUTS
CAPACITIVE
DAC
OUTPUT DATA
12-BIT PARALLEL
01128-012
Figure 12. Simplified Block Diagram of AD7492
Figure 13 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A. The comparator is held in a
balanced condition and the sampling capacitor acquires the
signal on V
IN
.
COMPARATOR
CONTROL LOGIC
AGND
2k
SW2
SW1
A
B
V
IN
CAPACITIVE
DAC
01128-013
Figure 13. ADC Acquisition Phase
Figure 14 shows the ADC during conversion. When conversion
starts, SW2 opens and SW1 moves to Position B, causing the
comparator to become unbalanced. The ADC then runs
through its successive approximation routine and brings the
comparator back into a balanced condition. When the
comparator is rebalanced, the conversion result is available in
the SAR register.
COMPARATOR
CONTROL LOGIC
AGND
SW2
SW1
A
B
2k
V
IN
CAPACITIVE
DAC
01128-014
Figure 14. ADC Conversion Phase
TYPICAL CONNECTION DIAGRAM
Figure 15 shows a typical connection diagram for the AD7492.
Conversion is initiated by a falling edge on
CONVST
. Once
CONVST
goes low the BUSY signal goes high, and at the end of
the conversion, the falling edge of BUSY is used to activate an
interrupt service routine. The
CS
and
RD
lines are then activated
in parallel to read the 12 data bits. The internal band gap
reference voltage is 2.5 V, providing an analog input range of 0 V
to 2.5 V, making the AD7492 a unipolar A/D. A capacitor with a
minimum capacitance of 100 nF is needed at the output of the
REF OUT pin as it stabilizes the internal reference value. It is
recommended to perform a dummy conversion after power-up as
the first conversion result could be incorrect. This also ensures
that the part is in the correct mode of operation. The
CONVST
pin should not be floating when power is applied, as a rising edge
on
CONVST
might not wake up the part.
In
Figure 15 the V
DRIVE
pin is tied to DV
DD
, which results in
logic output voltage values being either 0 V or DV
DD
. The
voltage applied to V
DRIVE
controls the voltage value of the output
logic signals and the input logic signals. For example, if DV
DD
is
supplied by a 5 V supply and V
DRIVE
by a 3 V supply, the logic
output voltage levels would be either 0 V or 3 V. This feature
allows the AD7492 to interface to 3 V parts while still enabling
the A/D to process signals at 5 V supply.
100nF
2.5V
0V TO 2.5V
1nF
AD7492
REF OUT
CS
BUSY
CONVST
RD
++
µC/µP
PARALLELED
INTERFACE
10µF
0.1µF 47µF
AV
DD
V
DRIVE
DV
DD
V
IN
NALOG
SUPPLY
2.7V TO 5.25V
PS/FS
0
1128-015
DB0 TO
DB9 (DB11)
Figure 15. Typical Connection Diagram
ADC TRANSFER FUNCTION
The output coding of the AD7492 is straight binary. The
designed code transitions occur at successive integer LSB values
(that is, 1 LSB, 2 LSB, etc.). The LSB size equals 2.5/4096 for the
AD7492. The ideal transfer characteristic for the AD7492 is
shown in
Figure 16.
AD7492
Rev. A | Page 14 of 24
111...111
111...110
111...000
011...111
000...010
000...001
000...000
ADC CODE
ANALOG INPUT
1LSB = V
REF
/4096
0V 1/2LSB +V
REF
–1LSB
01128-016
Figure 16. Transfer Characteristic for 12 Bits
AC ACQUISITION TIME
In ac applications, it is recommended to always buffer analog
input signals. The source impedance of the drive circuitry must
be kept as low as possible to minimize the acquisition time of
the ADC. Large values of impedance at the V
IN
pin of the ADC
cause the THD to degrade at high input frequencies.
Table 6. Dynamic Performance Specifications
Input
Buffers
SNR
500 kHz
THD
500 kHz
Typical Amplifier Current
Consumption
AD9631 69.5 80 17 mA
AD797 69.6 81.6 8.2 mA
DC ACQUISITION TIME
The ADC starts a new acquisition phase at the end of a
conversion and ends it on the falling edge of the
CONVST
signal. At the end of the conversion, there is a settling time
associated with the sampling circuit. This settling time lasts
120 ns. The analog signal on V
IN
is also acquired during this
settling time; therefore, the minimum acquisition time needed
is 120 ns.
Figure 17 shows the equivalent charging circuit for the sampling
capacitor when the ADC is in its acquisition phase. R3
represents the source impedance of a buffer amplifier or
resistive network, R1 is an internal switch resistance, R2 is for
bandwidth control, and C1 is the sampling capacitor. C2 is
back-plate capacitance and switch parasitic capacitance.
During the acquisition phase the sampling capacitor must be
charged to within 0.5 LSB of its final value.
R3
V
IN
R1
125
C1
22pF
C2
8pF
R2
636
0
1128-017
Figure 17. Equivalent Analog Input Circuit
ANALOG INPUT
Figure 18 shows the equivalent circuit of the analog input
structure of the AD7492. The two diodes, D1 and D2, provide
ESD protection for the analog inputs. The Capacitor C3 is
typically about 4 pF and can be primarily attributed to pin
capacitance. The Resistor R1 is an internal switch resistance.
This resistor is typically about 125 Ω. The Capacitor C1 is the
sampling capacitor while R2 is used for bandwidth control.
D1
D2
V
DD
R1
125
C1
22pF
C2
8pF
R2
636
V
IN
C3
4pF
01128-018
Figure 18. Equivalent Analog Input Circuit
PARALLEL INTERFACE
The parallel interface of the AD7492 is 12 bits wide. The output
data buffers are activated when both
CS
and
RD
are logic low. At
this point the contents of the data register are placed onto the data
bus.
Figure 19 shows the timing diagram for the parallel port.
Figure 20 shows the timing diagram for the parallel port when
CS
and
RD
are tied permanently low. In this setup, once the
BUSY line goes from high to low, the conversion process is
completed. The data is available on the output bus slightly
before the falling edge of BUSY.
Note that the data bus cannot change state while the A/D is
doing a conversion, as this would have a detrimental effect on
the conversion in progress. The data out lines go three-state
again when either the
RD
or
CS
line goes high. Thus the
CS
can
be tied low permanently, leaving the
RD
line to control
conversion result access. Please reference the V
DRIVE
section for
output voltage levels.
OPERATING MODES
The AD7492 has two possible modes of operation depending
on the state of the
CONVST
pulse at the end of a conversion,
Mode 1 and Mode 2.
Mode 1 (High-Speed Sampling)
In this mode of operation the
CONVST
pulse is brought high
before the end of conversion, that is, before BUSY goes low (see
Figure 20). If the
CONVST
pin is brought from high-to-low
while BUSY is high, the conversion is restarted. When
operating in this mode a new conversion should not be initiated
until 140 ns after BUSY goes low. This acquisition time allows
the track/hold circuit to accurately acquire the input signal. As
mentioned earlier, a read should not be done during a
conversion. This mode facilitates the fastest throughput times
for the AD7492.

AD7492ARUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 1MSPS 4mW Int Ref & Clk 12B Parallel
Lifecycle:
New from this manufacturer.
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