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AD7492ARUZ

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AD7492
Rev. A | Page 6 of 24
TIMING SPECIFICATIONS
V
DD
= 2.7 V to 5.25 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Table 3.
Limit at T
MIN
, T
MAX
Parameter AD7492/AD7492-4 AD7492-5
2
Unit Description
t
CONVERT
880 680 ns max
t
WAKEUP
20
3
20
3
μs max Partial Sleep Wake-Up Time
500 500 μs max Full Sleep Wake-Up Time
t
1
10 10 ns min
CONVST Pulse Width
t
2
10 10 ns max
CONVST to BUSY Delay, V
DD
= 5 V
40 N/A ns max
CONVST to BUSY Delay, V
DD
= 3 V
t
3
0 0 ns max
BUSY to
CS Setup Time
t
4
4
0 0 ns max
CS to RD Setup Time
t
5
20 20 ns min
RD Pulse Width
t
6
4
15 15 ns min
Data Access Time after Falling Edge of
RD
t
7
5
8 8 ns max
Bus Relinquish Time after Rising Edge of
RD
t
8
0 0 ns max
CS to RD Hold Time
t
9
120 120 ns min Acquisition Time
t
10
100 100 ns min Quiet Time
1
Sample tested @ 25°C to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V (see Figure 2).
2
The AD7492-5 is specified with V
DD
= 4.75 V to 5.25 V.
3
This is the time needed for the part to settle within 0.5 LSB of its stable value. Conversion can be initiated earlier than 20 μs, but there is no guarantee that the part
samples within 0.5 LSB of the true analog input value. Therefore, the user should not start conversion until after the specified time.
4
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V
5
t
7
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
7
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
1.6V
200µA
I
OL
TO OUTPUT
PIN
C
L
50pF
200µA
I
OH
0
1128-002
Figure 2. Load Circuit for Digital Output Timing Specifications
AD7492
Rev. A | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 4.
Parameter Ratings
AV
DD
to AGND/DGND −0.3 V to +7 V
DV
DD
to AGND/DGND −0.3 V to +7 V
V
DRIVE
to AGND/DGND −0.3 V to +7 V
AV
DD
to DV
DD
−0.3 V to +0.3 V
V
DRIVE
to DV
DD
−0.3 V to DV
DD
+ 0.3 V
AGND to DGND −0.3 V to +0.3 V
Analog Input Voltage to AGND −0.3 V to AV
DD
+ 0.3 V
Digital Input Voltage to DGND −0.3 V to DV
DD
+ 0.3 V
Input Current to Any Pin Except
Supplies
1
±10 mA
Operating Temperature Range
Commercial (A and B Versions) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
SOIC, TSSOP Package Dissipation 450 mW
θ
JA
Thermal Impedance 75°C/W (SOIC)
115°C/W (TSSOP)
θ
JC
Thermal Impedance 25°C/W (SOIC)
35°C/W (TSSOP)
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1
Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD7492
Rev. A | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7492
TOP VIEW
(Not to Scale)
DB9
DB10
(MSB) DB11
AV
DD
BUSY
PS/FS
REF OUT
CONVST
RD
AGND
CS
V
IN
DB8
DB7
DB6
V
DRIVE
DB0 (LSB)
DB1
DV
DD
DB2
DB3
DB5
DB4
DGND
01128-003
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin Mnemonic Function
1 to 3,
13 to 18,
22 to 24
DB11 to DB0
Data Bit 11 to Data Bit 0. Parallel digital outputs that provide the conversion result for the part. These are
three-state outputs that are controlled by
CS and RD. The output high voltage level for these outputs is
determined by the V
DRIVE
input.
4 AV
DD
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7492.
The AV
DD
and DV
DD
voltages should ideally be at the same potential and must not be more than 0.3 V apart,
even on a transient basis. This supply should be decoupled to AGND.
5 REF OUT Reference Out. The output voltage from this pin is 2.5 V ± 1%.
6 V
IN
Analog Input. Single-ended analog input channel. The input range is 0 V to REFIN. The analog input presents
a high dc input impedance.
7 AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7492. All analog input signals
should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
8
CS Chip Select. Active low logic input used in conjunction with RD to access the conversion result. The
conversion result is placed on the data bus following the falling edge of both
CS and RD. CS and RD are both
connected to the same AND gate on the input so the signals are interchangeable.
CS can be hardwired
permanently low.
9
RD Read Input. Logic input used in conjunction with CS to access the conversion result. The conversion result is
placed on the data bus following the falling edge of both
CS and RD. CS and RD are both connected to the
same AND gate on the input so the signals are interchangeable.
CS and RD can be hardwired permanently
low, in which case the data bus is always active and the result of the new conversion is clocked out slightly
before to the BUSY line going low.
10
CONVST Conversion Start Input. Logic input used to initiate conversion. The input track/hold amplifier goes from track
mode to hold mode on the falling edge of
CONVST and the conversion process is initiated at this point. The
conversion input can be as narrow as 10 ns. If the
CONVST input is kept low for the duration of conversion
and is still low at the end of conversion, the part automatically enters a sleep mode. The type of sleep mode is
determined by the PS/
FS pin. If the part enters a sleep mode, the next rising edge of CONVST wakes up the
part. Wake-up time depends on the type of sleep mode.
11
PS/
FS Partial Sleep/Full Sleep Mode. This pin determines the type of sleep mode the part enters if the CONVST pin is
kept low for the duration of the conversion and is still low at the end of conversion. In partial sleep mode the
internal reference circuit and oscillator circuit are not powered down and draws 250 μA maximum. In full
sleep mode all of the analog circuitry are powered down and the current drawn is negligible. This pin is
hardwired either high (DV
DD
) or low (GND).
12 BUSY
BUSY Output. Logic output indicating the status of the conversion process. The BUSY signal goes high after
the falling edge of
CONVST and stays high for the duration of the conversion. Once the conversion is
complete and the conversion result is in the output register, the BUSY line returns low. The track/hold returns
to track mode just prior to the falling edge of BUSY and the acquisition time for the part begins when BUSY
goes low. If the
CONVST input is still low when BUSY goes low, the part automatically enters its sleep mode
on the falling edge of BUSY.
19 DGND
Digital Ground. This is the ground reference point for all digital circuitry on the AD7492. The DGND and AGND
voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient
basis.
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AD7492ARUZ

Mfr. #:
Buy AD7492ARUZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 1MSPS 4mW Int Ref & Clk 12B Parallel
Lifecycle:
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