AD7492ARUZ Datasheet AD7492ARUZ, AD7492BRUZ-5, AD7492ARZ | P16-P18

AD7492

Rev. A | Page 15 of 24

BUSY

DBx

CONVST

CONVERT

01128-019

Figure 19. Parallel Port Timing

CONVST

BUSY

DBx

CONVERT

DATA N DATA N+1

01128-020

Figure 20. Parallel Port Timing with

and

Tied Low

Mode 2 (Partial or Full Sleep Mode)

Figure 21 shows the AD7492 in Mode 2 operation where the

ADC goes into either partial or full sleep mode after

conversion. The

CONVST

line is brought low to initiate a

conversion and remains low until after the end of the

conversion. If

CONVST

goes high and low again while BUSY is

high, the conversion is restarted. Once the BUSY line goes from

high-to-low, the

CONVST

line has its status checked and, if low,

the part enters a sleep mode. The type of sleep mode the

AD7492 enters depends on what way the PS/

pin is

hardwired. If the PS/

pin is tied high, the AD7492 enters

partial sleep mode. If the PS/

pin is tied low, the AD7492

enters full sleep mode.

The device wakes up again on the rising edge of the

CONVST

signal. From partial sleep the AD7492 is capable of starting

conversions typically 1 μs after the rising edge of

CONVST

. The

CONVST

line can go from high-to-low during the wake-up time,

but the conversion is still not initiated until after 1 μs. It is

recommended that the conversion should not be initiated until at

least 20 μs of the wake-up time has elapsed. This ensures that the

AD7492 has stabilized to within 0.5 LSB of the analog input value.

After 1 μs, the AD7492 has only stabilized to within approxi-

mately 3 LSB of the input value. From full sleep, this wake-up

time is typically 500 μs. In all cases the BUSY line only goes high

once

CONVST

goes low. Superior power performance can be

achieved in these modes of operation by waking up the AD7492

only to carry out a conversion. The optimum power performance

is obtained when using full sleep mode as the ADC comparator,

reference buffer, and reference circuit are powered down. While

in partial sleep mode, only the ADC comparator is powered

down and the reference buffer is put into a low power mode. The

100 nF capacitor on the REF OUT pin is kept charged up by the

reference buffer in partial sleep mode while in full sleep mode

this capacitor slowly discharges. This explains why the wake-up

time is shorter in partial sleep mode. In both sleep modes the

clock oscillator circuit is powered down.

AD7492

Rev. A | Page 16 of 24

CONVST

BUSY

DBx

WAKEUP

CONVERT

01128-021

Figure 21. Mode 2 Operation

DRIVE

The V

DRIVE

pin is used as the voltage supply to the digital output

drivers and the digital input circuitry. It is a separate supply

from AV

and DV

. The purpose of using a separate supply

for the digital input/output interface is that the user can vary

the output high voltage, V

, and the logic input levels, V

INH

and V

INL

, from the V

supply to the AD7492. For example, if

and DV

are using a 5 V supply, the V

DRIVE

pin can be

powered from a 3 V supply. The ADC has better dynamic

performance at 5 V than at 3 V, so operating the part at 5 V,

while still being able to interface to 3 V parts, pushes the

AD7492 to the top bracket of high performance 12-bit ADCs.

Of course, the ADC can have its V

DRIVE

and DV

pins

connected together and be powered from a 3 V or 5 V supply.

The trigger levels are V

DRIVE

× 0.7 and V

DRIVE

× 0.3 for the digital

inputs. The pins that are powered from V

DRIVE

are DB11 to DB0,

CONVST

, and BUSY.

PS/

As previously mentioned, the PS/

pin is used to control the

type of power-down mode that the AD7492 can enter into if

operated in Mode 2. This pin can be hardwired either high or

low, or even controlled by another device. It is important to

note that toggling the PS/

pin while in power-down mode

does not switch the part between partial sleep and full sleep

modes. To switch from one sleep mode to another, the AD7492

has to be powered up and the polarity of the PS/

pin changed.

It can then be powered down to the required sleep mode.

POWER-UP

It is recommended that the user performs a dummy conversion

after power-up, as the first conversion result could be incorrect.

This also ensures that the part is in the correct mode of

operation. The recommended power-up sequence is as follows:

1. GND

2. V

3. V

DRIVE

4. Digital Inputs

5. V

Power vs. Throughput

The two modes of operation for the AD7492 produces different

power vs. throughput performances, Mode 1 and Mode 2; see

the

Operating Modes section of the data sheet for more detailed

descriptions of these modes. Mode 2 is the sleep mode

(partial/full) of the part and it achieves the optimum power

performance.

Mode 1

Figure 22 shows the AD7492 conversion sequence in Mode 1

using a throughput rate of 500 kSPS. At 5 V supply, the current

consumption for the part when converting is 3 mA and the

quiescent current is 1.8 mA. The conversion time of 880 ns

contributes 6.6 mW to the overall power dissipation in the

following way:

(880 ns/2 μs) × (5 × 3 mA) = 6.6 mW

The contribution to the total power dissipated by the remaining

1.12 μs of the cycle is 5.04 mW

(1.12 μs/2 μs) × (5 × 1.8 mA) = 5.04 mW

Thus the power dissipated during each cycle is

6.6 mW + 5.04 mW = 11.64 mW

CONVST

BUSY

880ns

QUIESCENT

CONVERT

1.12µs

2µs

01128-022

Figure 22. Mode 1 Power Dissipation

AD7492

Rev. A | Page 17 of 24

Mode 2 (Full Sleep Mode)

Figure 23 shows the AD7492 conversion sequence in Mode 2,

full sleep mode, using a throughput rate of approximately

100 kSPS. At 5 V supply the current consumption for the part

when converting is 3 mA, while the full sleep current is 1 μA

maximum. The power dissipated during this power-down is

negligible and thus not worth considering in the total power

figure. During the wake-up phase, the AD7492 draws typically

1.8 mA. Overall power dissipated is

(880 ns/10 ms) × (5 × 3 mA) + (500 μs/10 ms) × (5 × 1.8 mA)

= 451.32 μW

CONVST

BUSY

880ns

9.5ms

10ms

QUIESCENT

CONVERT

500µs

WAKEUP

01128-023

Figure 23. Full Sleep Power Dissipation

Mode 2 (Partial Sleep Mode)

Figure 24 shows the AD7492 conversion sequence in Mode 2,

partial sleep mode, using a throughput rate of 1 kSPS. At 5 V

supply, the current consumption for the part when converting is

3 mA, while the partial sleep current is 250 μA maximum.

During the wake-up phase, the AD7492 typically draws 1.8 mA.

Power dissipated during wake-up and conversion is

(880 ns/1 ms) × (5 × 3 mA) + (20 μs/1 ms) × (5 × 1.8 mA) =

193.2 mW

Power dissipated during power-down is

(979 μs/1 ms) × (5 × 250 μA) = 1.22 mW

Overall power dissipated is

193.2 μW + 1.22 mW = 1.41 mW

CONVST

BUSY

880ns

1ms

QUIESCENT

CONVERT

20µs

WAKEUP

979µs

01128-024

Figure 24. Partial Sleep Power Dissipation

Figure 25, Figure 26, and Figure 27 show a typical graphical

representation of power vs. throughput for the AD7492 when in

Mode 1 @ 5 V and 3 V, Mode 2 in full sleep mode @ 5 V and 3

V, and Mode 2 in partial sleep mode @ 5 V and 3 V.

700

8004003002001000

POWER (mV)

THROUGHPUT (kHz)

500 600 900 1000

01128-025

Figure 25. Power vs. Throughput

(Mode 1 @ 5 V and 3 V)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

80403020100

POWER (mV)

THROUGHPUT (kHz)

50 60 90 100

01128-026

Figure 26. Power vs. Throughput

(Mode 2 in Full Sleep Mode @ 5 V and 3 V)

0.5

1.0

1.5

2.0

2.5

80403020100

POWER (mV)

THROUGHPUT (kHz)

50 60 90 100

01128-027

Figure 27. Power vs. Throughput

(Mode 2 in Partial Sleep Mode @ 5 V and 3 V)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

AD7492ARUZ

Mfr. #:

Buy AD7492ARUZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 1MSPS 4mW Int Ref & Clk 12B Parallel

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AD7492ARUZ

AD7492ARUZ

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