MT46H64M32L2JG-6 IT:A

‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR
SDRAM Addendum
Preliminary
PDF: 09005aef833508fb/Source: 09005aef83350d72 Micron Technology, Inc., reserves the right to change products or specifications without notice.
ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN
1 ©2008 Micron Technology, Inc. All rights reserved.
Mobile LPDDR
168-Ball Package-on-Package (PoP) TI OMAP™
MT46HxxxMxxLxJG
Features
Vdd/Vddq = 1.70–1.95V
Bidirectional data strobe per byte of data (DQS)
Internal, pipelined double data rate (DDR)
architecture; 2 data accesses per clock cycle
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
4 internal banks for concurrent operation
Data masks (DM) for masking write data—one mask
per byte
Programmable burst lengths (BL): 2, 4, 8, or 16
1
Concurrent auto precharge option is supported
Auto refresh and self refresh modes
1.8V LVCMOS-compatible inputs
On-chip temperature sensor to control self refresh
rate
Partial-array self refresh (PASR)
Deep power-down (DPD)
STATUS READ REGISTER (SRR) supported
2
Selectable output drive strength
Clock stop capability
64ms refresh
Notes: 1. Contact factory for availability.
2. Contact factory for remapped SRR output.
Options Marking
•Vdd/Vddq
1.8V/1.8V H
Configuration
128 Meg x 16 (32 Meg x 16 x 4
banks)
64 Meg x 32 (16 Meg x 32 x 4 banks)
64 Meg x 16 (16 Meg x 16 x 4 banks)
32 Meg x 32 (8 Meg x 32 x 4 banks)
128M16
64M32
64M16
32M32
Device version
Single die, standard addressing
2-die stack, standard addressing
LF
L2
Plastic “green” package
168-ball VFBGA (12mm x 12mm) JG
Timing – cycle time
5ns @ CL = 3
5.4ns @ CL = 3
6ns @ CL = 3
-5
-54
-6
Operating temperature range
Commercial (0° to +70°C)
Industrial (–40°C to +85°C)
None
IT
Table 1: Configuration Addressing
Architecture 128 Meg x 16 64 Meg x 32 64 Meg x 16 32 Meg x 32
Configuration
32 Meg x 16 x 4 banks 16 Meg x 32 x 4 banks 16 Meg x 16 x 4 banks 8 Meg x 32 x 4 banks
Refresh count
8K 8K 8K 8K
Row addressing
16K (A[13:0]) 8K (A[12:0]) 16K (A[13:0]) 8K (A[12:0])
Column addressing
1K (A[9:0]) 1K (A[9:0]) 1K (A[9:0]) 1K (A[9:0])
PDF: 09005aef833508fb/Source: 09005aef83350d72 Micron Technology, Inc., reserves the right to change products or specifications without notice.
ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN
2 ©2008 Micron Technology, Inc. All rights reserved.
168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR
SDRAM Addendum
Preliminary
Part Numbering Information - 168-Ball PoP
Micron
®
168-ball packaged LPDDR-SDRAM devices are available in several configura-
tions.
Figure 1: 168-Ball Part Number Chart
Device Marking
Due to the size of the package, the Micron-standard part number is not printed on the
top of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanu-
meric code is used. The abbreviated device marks are cross-referenced to the Micron
part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. To
view the location of the abbreviated mark on the device, refer to customer service note
CSN-11, “Product Mark/Label,” at www.micron.com/csn.
Table 2: 168-Ball Production Part Numbers
Part Numbers LPDDR Product Physical Part Marking
MT46H32M32LFJG-5:A 1Gb DDR, x32, 200 MHz
D9KFD
MT46H32M32LFJG-5 IT:A 1Gb DDR, x32, 200 MHz
D9KFC
MT46H32M32LFJG-54:A 1Gb DDR, x32, 185 MHz
D9KVC
MT46H32M32LFJG-54 IT:A 1Gb DDR, x32, 185 MHz
D9KVD
MT46H32M32LFJG-6:A 1Gb DDR, x32, 166 MHz
D9KNG
MT46H32M32LFJG-6 IT:A 1Gb DDR, x32, 166 MHz
D9KCK
MT46H64M32L2JG-5:A 2 x 1Gb DDR, x32, 200 MHz
D9KDK
MT46H64M32L2JG-5 IT:A 2 x 1Gb DDR, x32, 200 MHz
D9KDG
MT46H64M32L2JG-54:A 2 x 1Gb DDR, x32, 185 MHz
D9KDJ
MT46H64M32L2JG-54 IT:A 2 x 1Gb DDR, x32, 185 MHz
D9KVB
MT46H64M32L2JG-6:A 2 x 1Gb DDR, x32, 166 MHz
D9KCX
MT46H64M32L2JG-6 IT:A 2 x 1Gb DDR, x32, 166 MHz
D9KCW
Micron Technology
Product Family
46 = LPDDR-SDRAM
Operating Voltage
H = 1.8V/1.8V
Configuration
128 Meg x 16
64 Meg x 32
64 Meg x 16
32 Meg x 32
Device Version
LF = Single die, standard addressing
L2 = Dual die, standard addressing
Design Revision
:A = First generation
Operating Temperature
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Cycle Time
-5 = 5ns
t
CK CL = 3
-54 = 5.4ns
t
CK CL = 3
-6 = 6ns
t
CK CL = 3
Package Codes
JG = 12mm x 12mm VFBGA “green”
MT 46 H 32M32 LF JG -6 IT :A
PDF: 09005aef833508fb/Source: 09005aef83350d72 Micron Technology, Inc., reserves the right to change products or specifications without notice.
ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN
3 ©2008 Micron Technology, Inc. All rights reserved.
168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR
SDRAM Addendum
Preliminary
General Description
The 1Gb Mobile LPDDR die contained within this package is a high-speed CMOS,
dynamic random access memory containing 1,073,741,824 bits. It is internally config-
ured as a quad-bank DRAM. Each of the x16’s 268,435,456-bit banks is organized as
16,384 rows by 1024 columns by 16 bits. Each of the x32’s 268,435,456-bit banks is orga-
nized as 8192 rows by 1024 columns by 32 bits.
Figure 2: Functional Block Diagram (64 Meg x 16)
Row-
address
MUX
Control
logic
Column-
address
counter/
latch
Standard mode
register
Extended mode
register
Command
decode
Address
BA0, BA1
CKE
CK#
CK
CS#
WE#
CAS#
RAS#
Address
register
I/O gating
DM mask logic
Column
decoder
Bank 0
memory
array
Bank 0
row-
address
latch
and
decoder
Bank
control
logic
Bank 1
Bank 2
Bank 3
Refresh
counter
16
16
16
2
Input
registers
2
2
2
2
RCVRS
2
32
32
2
2
4
32
CK
out
Data
DQS
Mask
Data
CK
CK
in
DRVRS
MUX
DQS
generator
16
16
16
16
16
32
DQ0–
DQ15
LDQS,
UDQS
2
Read
latch
Write
FIFO
and
drivers
1
Col 0
Col 0
Sense amplifiers
LDM,
UDM
CK

MT46H64M32L2JG-6 IT:A

Mfr. #:
Manufacturer:
Micron
Description:
IC DRAM 2G PARALLEL 168VFBGA
Lifecycle:
New from this manufacturer.
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