PDF: 09005aef833508fb/Source: 09005aef83350d72 Micron Technology, Inc., reserves the right to change products or specifications without notice.
ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN
7 ©2008 Micron Technology, Inc. All rights reserved.
168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR
SDRAM Addendum
Preliminary
Notes: 1. Balls marked RFU may or may not be connected internally. These balls should not be used.
Contact factory for details.
Table 3: x16/x32 LPDDR Ball Descriptions
x16 Balls x32 Balls Symbol Type Description
W23, W22, V23, V22,
U23, U22, T23, T22, R23,
R22, P23, P22, N23, N22
W22, V23, V22, U23,
U22, T23, T22, R23, R22,
P23, P22, N23, N22
A[13:0]
(x16)
A[12:0]
(x32)
Input
Address inputs: Specify row/column addresses.
Also used to load the mode registers. The
maximum address is determined by density
and configuration. Consult the product data
sheet for the maximum address for a given
density and configuration.
Unused address pins become RFU
1
.
AB21, AC21 AB21, AC21 BA0, BA1 Input
Bank address inputs: Specifies one of the 4
banks.
L22 L22 CAS# Input
Column select: Specifies the command to
execute.
A11, B11 A11, B11 CK, CK#
CK is the system clock. CK and CK# are
differential clock inputs. All address and
control signals are sampled and referenced on
the crossing of the rising edge of CK with the
falling edge of CK#.
J22, J23 J22, J23 CKE0, CKE1 Input
Clock enable:
CKE0 is used for a single LPDDR product.
CKE1 is used for dual LPDDR products and is
considered RFU for single products.
M22, M23 M22, M23 CS0#, CS1# Input
Chip select:
CS0# is used for a single LPDDR product.
CS1# is used for dual LPDDR products and is
considered RFU for single products
A17, A6 A20, A6, A17, C1 LDM, UDM
(x16)
DM[3:0]
(x32)
Input
Data mask: Determines which bytes are
written during WRITE operations.
For x16 LPDDR, unused DM balls become
DNU.
L23 L23 RAS# Input
Row select: Specifies the command to
execute.
K23 K23 WE# Input
Write enable: Specifies the command to
execute.
B3, A3, B5, A5, B8, A8,
B9, A9, B13, A13, B14,
A14, B16, A16, B19, A19
G23, G22, E23, E22, D23,
D22, A21, B21, A9, B9,
A8, B8, A5, B5, A3, B3,
A19, B19, A16, B16, A14,
B14, A13, B13, D1, D2,
F1, F2, G1, G2, J1, J2
DQ[15:0]
(x16)
DQ[31:0]
(x32)
Input/
output
Data bus: Data inputs/outputs. DQ[31:16] are
DNU for x16 LPDDR devices.
Note: For dual-die devices, the I/O capacitance
will be twice the value shown in the packaged
data sheet.
B17, B6 B20, B6, B17, C2 LDQS, UDQS
(x16)
DQS[3:0]
(x32)
Input/
output
Data strobe: Coordinates read/write transfers
of data; one DQS per DQ byte.
AC14 AC14 TQ Output
Temperature sensor output: TQ HIGH when
LPDDR T
J
exceeds 85°C.
A12, H23, K1, Y23, AA23 A12, H23, K1, Y23, AA23 Vdd Supply
Vdd: LPDDR power supply.
A4, A7, A10, A15, A18,
C23, E1, F23, H1
A4, A7, A10, A15, A18,
C23, E1, F23, H1
Vddq Supply
Vddq: LPDDR I/O power supply.
