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MT46H64M32L2JG-6 IT:A

P1-P3P4-P6P7-P9P10-P12
PDF: 09005aef833508fb/Source: 09005aef83350d72 Micron Technology, Inc., reserves the right to change products or specifications without notice.
ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN
4 ©2008 Micron Technology, Inc. All rights reserved.
168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR
SDRAM Addendum
Preliminary
Figure 3: Functional Block Diagram (32 Meg x 32)
RAS#
CAS#
Row-
address
MUX
CK
CS#
WE#
CK#
Control
logic
Column-
address
counter/
latch
Standard mode
register
Extended mode
register
Command
decode
Address,
BA0, BA1
CKE
Address
register
I/O gating
DM mask logic
Bank 0
memory
array
Bank 0
row-
address
latch
and
decoder
Bank
control
logic
Bank 1
Bank 2
Bank 3
Refresh
counter
32
2
2
32
32
4
Input
registers
4
4
4
4
RCVRS
4
64
64
8
64
CK
out
Data
DQS
Mask
Data
CK
CK
in
DRVRS
MUX
DQS
generator
32
32
32
32
32
64
DQ0–
DQ31
DQS0,
DQS1,
DQS2,
DQS3
4
Read
latch
Write
FIFO
and
drivers
1
Col 0
Col 0
Sense amplifiers
DM0,
DM1,
DM2,
DM3
CK
Column
decoder
PDF: 09005aef833508fb/Source: 09005aef83350d72 Micron Technology, Inc., reserves the right to change products or specifications without notice.
ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN
5 ©2008 Micron Technology, Inc. All rights reserved.
168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR
SDRAM Addendum
Preliminary
Ball Assignments and Descriptions
Figure 4: 168-Ball VFBGA (x32) Ball Assignments
Notes: 1. Although not bonded to the die, these pins may be connected on the package substrate.
1
DNU
DNU
DM0
DQ7
V
ddq
DQ5
DQ3
V
ddq
DQ1
V
dd
NC
1
NC
NC
NC
1
NC
NC
NC
1
NC
NC
NC
NC
1
DNU
DNU
1
2
DNU
DNU
DQS0
DQ6
Vssq
DQ4
DQ2
Vssq
DQ0
Vss
Vss
NC
NC
Vss
NC
NC
Vss
NC
NC
NC
Vss
DNU
DNU
2
4
V
ddq
Vssq
NC
NC
4
3
DQ17
DQ16
INC
NC
3
5
DQ19
DQ18
Vss
NC
1
5
6
DM2
DQS2
NC
NC
6
7
V
ddq
Vssq
NC
NC
7
8
DQ21
DQ20
Vss
NC
1
8
12
V
dd
Vss
NC
NC
12
13
DQ9
DQ8
Vss
NC
1
13
14
DQ11
DQ10
Vss
TQ
14
15
V
ddq
Vssq
NC
NC
15
16
DQ13
DQ12
NC
NC
16
17
DM1
DQS1
NC
NC
17
18
V
ddq
Vssq
NC
NC
18
19
DQ15
DQ14
NC
NC
19
20
DM3
DQS3
Vss
NC
20
21
DQ25
DQ24
BA0
BA1
21
22
DNU
DNU
Vssq
DQ26
DQ28
Vssq
DQ30
Vss
CKE0
Vss
CAS#
CS0#
A0
A2
A4
A6
A8
A10
A12
RFU
Vss
DNU
DNU
22
23
DNU
DNU
V
ddq
DQ27
DQ29
V
ddq
DQ31
V
dd
CKE1
WE#
RAS#
CS1#
A1
A3
A5
A7
A9
A11
RFU
V
dd
Vdd
DNU
DNU
23
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
A
A
AB
AC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
Top View – Ball Down
LPDDR Supply Ground
9
DQ23
DQ22
NC
NC
9
10
V
ddq
Vssq
NC
NC
10
11
CK
CK#
NC
NC
11
PDF: 09005aef833508fb/Source: 09005aef83350d72 Micron Technology, Inc., reserves the right to change products or specifications without notice.
ddr_mobile_sdram_only_168b_pop.fm - Rev. B 01/09 EN
6 ©2008 Micron Technology, Inc. All rights reserved.
168-Ball x16, x32 Mobile LPDDR PoP (TI OMAP)Mobile DDR
SDRAM Addendum
Preliminary
Figure 5: 168-Ball VFBGA (x16) Ball Assignments
Notes: 1. Although not bonded to the die, these pins may be connected together on the package
substrate.
1
DNU
DNU
DNU
DNU
Vddq
DNU
DNU
Vddq
DNU
Vdd
NC
1
NC
NC
NC
1
NC
NC
NC
1
NC
NC
NC
NC
1
DNU
DNU
1
2
DNU
DNU
DNU
DNU
Vssq
DNU
DNU
Vssq
DNU
Vss
Vss
NC
NC
Vss
NC
NC
Vss
NC
NC
NC
Vss
DNU
DNU
2
4
Vddq
Vssq
NC
NC
4
3
DQ14
DQ15
NC
NC
3
5
DQ12
DQ13
Vss
NC
1
5
6
UDM
UDQS
NC
NC
6
7
Vddq
Vssq
NC
NC
7
8
DQ10
DQ11
Vss
NC
1
8
12
Vdd
Vss
NC
NC
12
13
DQ6
DQ7
Vss
NC
1
13
14
DQ4
DQ5
Vss
TQ
14
15
Vddq
Vssq
NC
NC
15
16
DQ2
DQ3
NC
NC
16
17
LDM
LDQS
NC
NC
17
18
Vddq
Vssq
NC
NC
18
19
DQ0
DQ1
NC
NC
19
20
DNU
DNU
Vss
NC
20
21
DNU
DNU
BA0
BA1
21
22
DNU
DNU
Vssq
DNU
DNU
Vssq
DNU
Vss
CKE0
Vss
CAS#
CS0#
A0
A2
A4
A6
A8
A10
A12
RFU
Vss
DNU
DNU
22
23
DNU
DNU
Vddq
DNU
DNU
Vddq
DNU
Vdd
CKE1
WE#
RAS#
CS1#
A1
A3
A5
A7
A9
A11
A13
Vdd
Vdd
DNU
DNU
23
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
A
A
AB
AC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
Top View – Ball Down
9
DQ8
DQ9
NC
NC
9
10
Vddq
Vssq
NC
NC
10
11
CK
CK#
NC
NC
11
LPDDR Supply Ground
P1-P3P4-P6P7-P9P10-P12

MT46H64M32L2JG-6 IT:A

Mfr. #:
Buy MT46H64M32L2JG-6 IT:A
Manufacturer:
Micron
Description:
IC DRAM 2G PARALLEL 168VFBGA
Lifecycle:
New from this manufacturer.
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