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CYDMX128A16-65BVXIT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
CYDMX256A16/CYDMX256B16
CYDMX128A16/CYDMX128B16
CYDMX064A16/CYDMX064B16
Document Number: 001-08090 Rev. *I Page 10 of 25
Electrical Characteristics for V
CC
= 2.5 V
Over the Operating Range
Parameter
Description
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16
Unit
–65 –65 –90
P1 IO
Voltage
P2 IO
Voltage
Min Typ Max Min Typ Max Min Typ Max
V
OH
Output HIGH voltage
(I
OH
= –2 mA)
2.5 V (any port) 2.0 – – 2.0 – – 2.0 – – V
3.0 V (any port) 2.1 – – 2.1 – – 2.1 – – V
V
OL
Output LOW voltage
(I
OL
= 2 mA
2.5 V (any port) – – 0.4 – – 0.4 – – 0.4 V
3.0 V (any port) – – 0.4 – – 0.4 – – 0.4 V
V
OL
ODR
ODR Output LOW voltage
(I
OL
= 8 mA
2.5 V (any port) – – 0.2 – – 0.2 – – 0.2 V
3.0 V (any port) – – 0.2 – – 0.2 – – 0.2 V
V
IH
Input HIGH voltage 2.5 V (any port) 1.7 – V
DDIO
+ 0.3
1.7 – V
DDIO
+ 0.3
1.7 – V
DDIO
+ 0.3
V
3.0 V (any port) 2.0 – V
DDIO
+ 0.2
2.0 – V
DDIO
+ 0.2
2.0 – V
DDIO
+ 0.2
V
V
IL
Input LOW voltage 2.5 V (any port) –0.3 – 0.6 –0.3 – 0.6 –0.3 – 0.6 V
3.0 V (any port) –0.2 – 0.7 –0.2 – 0.7 –0.2 – 0.7 V
I
OZ
Output leakage current 2.5 V 2.5 V –1 – 1 –1 – 1 –1 – 1 A
3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A
I
CEX
ODR
ODR output leakage current.
V
OUT
= V
CC
2.5 V 2.5 V –1 – 1 –1 – 1 –1 – 1 A
3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A
I
IX
Input leakage current 2.5 V 2.5 V –1 – 1 –1 – 1 –1 – 1 A
3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A
I
CC
Operating current
(V
CC
= Max, I
OUT
= 0 mA)
outputs disabled
Ind. 2.5 V 2.5 V – 39 55 – 39 55 – 28 40 mA
I
SB1
Standby current
(both ports TTL level)
CE#L and
CE#R V
CC
– 0.2,
f = f
MAX
Ind.2.5 V2.5 V–68–68–68A
I
SB2
Standby current
(one port TTL level) CE#L
or CE#R V
IH
,
f = f
MAX
Ind. 2.5 V 2.5 V – 21 30 – 21 30 – 18 25 mA
I
SB3
Standby current
(both ports CMOS level)
CE#L and
CE#R V
CC
 0.2 V, f = 0
Ind.2.5 V2.5 V–46–46–46A
I
SB4
Standby current
(one port CMOS level)
CE#L or CE#R V
IH
,
f = f
MAX
[21]
Ind. 2.5 V 2.5 V – 21 30 – 21 30 – 18 25 mA
Note
21. f
MAX
= 1/t
RC
= All inputs cycling at f = 1/t
RC
(except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby I
SB3
.
CYDMX256A16/CYDMX256B16
CYDMX128A16/CYDMX128B16
CYDMX064A16/CYDMX064B16
Document Number: 001-08090 Rev. *I Page 11 of 25
Electrical Characteristics for 3.0 V
Over the Operating Range
Parameter
Description
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16
Unit
–65 –65 –90
P1 IO
Voltage
P2 IO
Voltage
Min Typ Max Min Typ Max Min Typ Max
V
OH
Output HIGH voltage (I
OH
= –2 mA) 3.0 V (any port) 2.1 – – 2.1 – – 2.1 – – V
V
OL
Output LOW voltage (I
OL
= 2 mA 3.0 V (any port) – – 0.4 – – 0.4 – – 0.4 V
V
OL
ODR
ODR output LOW voltage (I
OL
= 8 mA 3.0 V (any port) – – 0.2 – – 0.2 – – 0.2 V
V
IH
Input HIGH voltage 3.0 V (any port) 2.0 – V
DDIO
+ 0.2
2.0 – V
DDIO
+ 0.2
2.0 – V
DDIO
+ 0.2
V
V
IL
Input LOW voltage 3.0 V (any port) –0.2 – 0.7 –0.2 – 0.7 –0.2 – 0.7 V
I
OZ
Output leakage current 3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A
I
CEX
ODR
ODR output leakage current.
V
OUT
= V
CC
3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A
I
IX
Input leakage current 3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A
I
CC
Operating current
(V
CC
= Max, I
OUT
= 0 mA) outputs
disabled
Ind. 3.0 V 3.0 V – 49 70 – 49 70 – 42 60 mA
I
SB1
Standby current
(both ports TTL level)
CE#L and CE#R V
CC
– 0.2,
f = f
MAX
Ind. 3.0 V 3.0 V 7 10 7 10 7 10 A
I
SB2
Ind. 3.0 V 3.0 V 28 40 28 40 25 35 mA
I
SB3
Standby current
(one port TTL level)
CE#L or CE#R V
IH
, f = f
MAX
Ind. 3.0 V 3.0 V 6 8 6 8 6 8 A
I
SB4
Ind. 3.0 V 3.0 V 28 40 28 40 25 35 mA
Capacitance
Parameter
[22]
Description Test Conditions Max Unit
C
IN
Input capacitance T
A
= 25 °C, f = 1 MHz, V
CC
= 3.0 V 9 pF
C
OUT
Output capacitance 10 pF
Note
22. Tested initially and after any design or process changes that may affect these parameters.
CYDMX256A16/CYDMX256B16
CYDMX128A16/CYDMX128B16
CYDMX064A16/CYDMX064B16
Document Number: 001-08090 Rev. *I Page 12 of 25
Figure 2. AC Test Loads and Waveforms
1.8 V
GND
90%
90%
10%
10%
ALL INPUT PULSES
(a) Normal Load
R1
3.0 V/2.5 V/1.8 V
OUTPUT
R2
C = 30 pF
V
TH
= 0.8 V
OUTPUT
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay (Load 2)
R1
R2
3.0 V/2.5 V/1.8 V
OUTPUT
R
TH
= 6 k
3 ns
3 ns
including scope and jig)
(Used for t
LZ
, t
HZ
, t
HZWE
, and t
LZWE
3.0 V/2.5 V 1.8 V
R1 1022
13500
R2 792 10800
C = 30 pF
C = 5 pF
Switching Characteristics for V
CC
= 1.8 V
Over the Operating Range
[23]
Parameter Description
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16
Unit
–65 –65 –90
Min Max Min Max Min Max
AD Mux Port Read Cycle
[24]
t
RC
Read cycle time 65 – 65 – 90 – ns
t
ACC1
Random access ADV# Low to data valid – 65 – 65 – 90 ns
t
ACC2
Random access Address to data valid – 65 – 65 – 90 ns
t
ACC3
Random access CS# to data valid – 65 – 65 – 90 ns
t
AVDA
Random access ADV# High to data valid – 35 – 35 – 50 ns
t
AVD
ADV# low pulse 15 – 15 – 20 – ns
t
AVDS
Address setup to ADV# rising edge 15 – 15 – 20 – ns
t
AVDH
Address hold from ADV# rising edge 3 – 3 – 5 – ns
t
CSS
CS# setup to ADV# rising edge 7 – 7 – 10 – ns
t
OE
OE# Low to data valid – 35 – 35 – 50 ns
t
LZOE
[25]
OE# Low to IO Low Z 3 – 3 – 5 – ns
t
HZOE
OE# High to IO High Z – 15 – 15 – 25 ns
t
HZCS
CS# High to IO High Z – 15 – 15 – 25 ns
t
DBE
UB#/LB# Low to IO Valid – 35 – 35 – 50 ns
t
LZBE
UB#/LB# Low to IO Low Z 3 – 3 – 5 – ns
t
HZBE
UB#/LB# High to IO High Z – 15 – 15 – 25 ns
t
AVOE
ADV# High to OE# Low 0 – 0 – 0 – ns
Notes
23. All timing parameters are measured with Load 2 specified in Figure 2.
24. AD Mux port timing applies to left AD Mux port and right port configured to AD Mux port.
25. This parameter is guaranteed by not tested.
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CYDMX128A16-65BVXIT

Mfr. #:
Buy CYDMX128A16-65BVXIT
Manufacturer:
Cypress Semiconductor
Description:
SRAM MoBLADM DP,x16,128Kb 65 or 90ns access
Lifecycle:
New from this manufacturer.
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