CYDMX128A16-65BVXIT Datasheet CYDMX256A16-65BVXI, CYDMX128A16-65BVXIT, CYDMX128A16-65BVXI | P7-P9

CYDMX256A16/CYDMX256B16

CYDMX128A16/CYDMX128B16

CYDMX064A16/CYDMX064B16

Document Number: 001-08090 Rev. *I Page 7 of 25

Table 3. Interrupt Operation Example (Assumes BUSY#L

= BUSY#R = HIGH)

Function

Left Port Right Port

WE#L CS#L OE#L AddressL INT#L WE#R CS#R OE#R AddressR INT#R

Set Right INT#R Flag L L X 0x3FFF

[7]

XXXX X L

Reset Right INT#R Flag X X X X X X L L 0x3FFF

[7]

Set Left INT#L Flag X X X X L L L X 0x3FFE

[8]

Reset Left INT#L Flag X L L 0x3FFE

[8]

HXXX X X

Table 4. Arbitration Winning Port

CS#L CS#R

Address Match

Left/Right Port

BUSY#L BUSY#R Function

X X No Match H H Normal

HX Match HH Normal

XH Match HH Normal

L L Match See Note

[9]

See Note

[9]

Write Inhibit

[10]

Table 5. Input Read Register Operation

[11]

SFEN# CS# WE# OE# UB# LB# ADDR IO

–IO

Mode

HLHLLLx0000-MaxVALID

[12]

VALID

[12]

Standard Memory Access

L L H L X L x0000 VALID

[13]

X IRR Read

Table 6. Output Drive Register

[15]

SFEN# CS# WE# OE# UB# LB# ADDR IO

–IO

Mode

HLHX

[16]

[12]

x0000-Max VALID

[12]

VALID

[12]

Standard Memory Access

LLLXXLx0001VALID

[13]

X ODR Write

[17]

LLHLXLx0001VALID

[13]

X ODR Read

Notes

7. 0x3FFF for CYDMX256A16 and CYDMX256B16, 0x1FFF for CYDMX128A16 and CYDMX128B16, 0xFFF for CYDMX064A16 and CYDMX064B16.

8. 0x3FFE for CYDMX256A16 and CYDMX256B16, 0x1FFE for CYDMX128A16 and CYDMX128B16, 0xFFE for CYDMX064A16 and CYDMX064B16.

9. If it meets tPS, "L" if the CS# and address of the opposite port become stable BEFORE the current port; "H" if the CS# and address of the opposite port become

stable AFTER the current port. If tPS is not met, either BUSY#L or BUSY#R results “L”. BUSY#L and BUSY#R cannot be “L” simultaneously.

10. Write operations to the left port are internally ignored when BUSY#L is driving LOW regardless of actual logic level on the pin; Write operations to the right port are

internally ignored when BUSY#R is driving LOW regardless of actual logic level on the pin.

11. SFEN# = V

for IRR reads.

12. UB# or LB# = V

. If LB# = V

, then IO<7:0> are valid. If UB# = V

then IO<15:8> are valid.

13. LB# must be active (LB# = V

) for these bits to be valid.

14. SFEN# active when either CS#L = V

or CS#R = V

. It is inactive when CS#L = CS#R = V

15. SFEN# = V

for ODR reads and writes.

16. Output enable must be low (OE# = V

) during reads for valid data to be output.

17. During ODR writes data is also written to the memory.

CYDMX256A16/CYDMX256B16

CYDMX128A16/CYDMX128B16

CYDMX064A16/CYDMX064B16

Document Number: 001-08090 Rev. *I Page 8 of 25

Maximum Ratings

Exceeding maximum ratings

[18]

may shorten the useful life of the

device. User guidelines are not tested.

Storage Temperature................................ –65 °C to +150 °C

Ambient Temperature with

Power Applied .......................................... –55 °C to +125 °C

Supply Voltage to Ground Potential..............–0.5 V to +3.3 V

DC Voltage Applied to

Outputs in High Z State ....................... –0.5 V to V

+ 0.5 V

DC Input Voltage

[19]

.............................–0.5 V to V

+ 0.5 V

Output Current into Outputs (LOW)............................. 90 mA

Static Discharge Voltage......................................... > 2000 V

Latch up Current.................................................... > 200 mA

Operating Range

Range Ambient Temperature V

Industrial –40 °C to +85 °C 1.8 V ± 100 mV

2.5 V ± 100 mV

3.0 V ± 300 mV

Electrical Characteristics for V

= 1.8 V

Over the Operating Range

Parameter

Description

CYDMX256A16

CYDMX128A16

CYDMX256B16

CYDMX128B16

CYDMX064B16

CYDMX256A16

CYDMX128A16

CYDMX064A16

Unit

–65 –65 –90

P1 IO

Voltage

P2 IO

Voltage

Min Typ Max Min Typ Max Min Typ Max

Output HIGH voltage

= –100 A)

1.8 V (any port) V

DDIO

– 0.2

––V

DDIO

– 0.2

––V

DDIO

– 0.2

––V

Output HIGH voltage (I

= –2 mA) 2.5 V (any port) 2.0 – – 2.0 – – 2.0 – – V

Output HIGH voltage (I

= –2 mA) 3.0 V (any port) 2.1 – – 2.1 – – 2.1 – – V

Output LOW voltage (I

= 100 A 1.8 V (any port) – – 0.2 – – 0.2 – – 0.2 V

Output HIGH voltage (I

= 2 mA) 2.5 V (any port) – – 0.4 – – 0.4 – – 0.4 V

Output HIGH voltage (I

= 2 mA) 3.0 V (any port) – – 0.4 – – 0.4 – – 0.4 V

ODR

ODR output LOW voltage

= 8 mA

1.8 V (any port) – – 0.2 – – 0.2 – – 0.2 V

2.5 V (any port) – – 0.2 – – 0.2 – – 0.2 V

3.0 V (any port) – – 0.2 – – 0.2 – – 0.2 V

Input HIGH voltage 1.8 V (any port) 1.2 – V

DDIO

+ 0.2

1.2 – V

DDIO

+ 0.2

1.2 – V

DDIO

+ 0.2

2.5 V (any port) 1.7 – V

DDIO

+ 0.3

1.7 – V

DDIO

+ 0.3

1.7 – V

DDIO

+ 0.3

3.0 V (any port) 2.0 – V

DDIO

+ 0.2

2.0 – V

DDIO

+ 0.2

2.0 – V

DDIO

+ 0.2

Input LOW voltage 1.8 V (any port) –0.2 – 0.4 –0.2 – 0.4 –0.2 – 0.4 V

2.5 V (any port) –0.3 – 0.6 –0.3 – 0.6 –0.3 – 0.6 V

3.0 V (any port) –0.2 – 0.7 –0.2 – 0.7 –0.2 – 0.7 V

Output leakage current 1.8 V 1.8 V –1 – 1 –1 – 1 –1 – 1 A

2.5 V 2.5 V –1 – 1 –1 – 1 –1 – 1 A

3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A

CEX

ODR

ODR output leakage current. V

OUT

= V

DDIO

1.8 V 1.8 V –1 – 1 –1 – 1 –1 – 1 A

2.5 V 2.5 V –1 – 1 –1 – 1 –1 – 1 A

3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A

Notes

18. The voltage on any input or IO pin cannot exceed the power pin during power-up.

19. Pulse width < 20 ns.

CYDMX256A16/CYDMX256B16

CYDMX128A16/CYDMX128B16

CYDMX064A16/CYDMX064B16

Document Number: 001-08090 Rev. *I Page 9 of 25

Input leakage current 1.8 V 1.8 V –1 – 1 –1 – 1 –1 – 1 A

2.5 V 2.5 V –1 – 1 –1 – 1 –1 – 1 A

3.0 V 3.0 V –1 – 1 –1 – 1 –1 – 1 A

Operating current

= Max, I

OUT

= 0 mA)

outputs disabled

Ind. 1.8 V 1.8 V – 25 40 – 25 40 – 15 25 mA

SB1

Standby current

(both ports TTL level)

CE#L and CE#R  V

– 0.2,

f = f

MAX

Ind. 1.8 V 1.8 V – 2 6 – 2 6 – 2 6 A

SB2

Standby current

(One Port TTL level)

CE#L or CE#R  V

, f = f

MAX

Ind. 1.8 V 1.8 V – 8.5 18 – 8.5 18 – 8.5 14 mA

SB3

Standby current

(both ports CMOS level) CE#L

and CE#R  V

 0.2 V, f = 0

Ind. 1.8 V 1.8 V – 2 6 – 2 6 – 2 6 A

SB4

Standby current

(one port CMOS level)

CE#L or CE#R  V

f = f

MAX

[20]

Ind. 1.8 V 1.8 V – 8.5 18 – 8.5 18 – 8.5 14 mA

Electrical Characteristics for V

= 1.8 V (continued)

Over the Operating Range (continued)

Parameter

Description

CYDMX256A16

CYDMX128A16

CYDMX256B16

CYDMX128B16

CYDMX064B16

CYDMX256A16

CYDMX128A16

CYDMX064A16

Unit

–65 –65 –90

P1 IO

Voltage

P2 IO

Voltage

Min Typ Max Min Typ Max Min Typ Max

Note

20. f

MAX

= 1/t

= All inputs cycling at f = 1/t

(except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby

SB3

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

CYDMX128A16-65BVXIT

Mfr. #:

Buy CYDMX128A16-65BVXIT

Manufacturer:

Cypress Semiconductor

Description:

SRAM MoBLADM DP,x16,128Kb 65 or 90ns access

Lifecycle:

New from this manufacturer.

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CYDMX128A16-65BVXIT

CYDMX128A16-65BVXIT

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