CYDMX256A16/CYDMX256B16
CYDMX128A16/CYDMX128B16
CYDMX064A16/CYDMX064B16
Document Number: 001-08090 Rev. *I Page 16 of 25
Figure 5. ADM Port Write Cycle (Either Port Access, CS# Controlled, OE# High)
Figure 6. Standard Port Read Cycle (Right Port Access, WE# High)
A
ddr1<15..0>
I/O
[
15:0
]
A
DV#
OE
#
W
E#
CS
#
WData1<15..0>
t
A
VW
E
t
WRL
t
SD
t
HD
t
A
VD
t
A
VD
S
t
A
VDH
t
CSS
t
SC
S
UB#, LB#
t
BW
Valid Address
A
ddress
OE
#
W
E#
CS
#
t
RC
t
HZC
S
t
HZO
E
UB#, LB#
t
HZB
E
Data Ou
t
Valid Data
t
OHA
t
AA
t
A
C
S
t
DO
E
t
LZO
E
t
LZCS
t
A
BE
t
LZBE
CYDMX256A16/CYDMX256B16
CYDMX128A16/CYDMX128B16
CYDMX064A16/CYDMX064B16
Document Number: 001-08090 Rev. *I Page 17 of 25
Figure 7. Standard Port Write Cycle (Right Port Access, WE# Controlled)
Figure 8. Standard Port Write Cycle (Right Port Access, CS# Controlled)
Valid Address
A
ddress
OE#
W
E
#
CS#
t
WC
t
LZWE
UB#, LB# t
BW
Data
Valid Data
t
AW
t
SA
t
WRL
t
SD
t
HD
t
HZW
E
t
HA
Valid Address
A
ddress
OE
#
W
E#
CS
#
t
WC
t
LZCS
UB#, LB# t
BW
Data
Valid Data
t
AW
t
SA
t
WRL
t
SD
t
HD
t
HZW
E
t
HA
t
SC
S
CYDMX256A16/CYDMX256B16
CYDMX128A16/CYDMX128B16
CYDMX064A16/CYDMX064B16
Document Number: 001-08090 Rev. *I Page 18 of 25
Figure 9. Arbitration Timing
Figure 10. Arbitration Timing (Address Controlled with Left ADM and Right Standard Configuration
A
ddress Match
A
ddress L & R
CS#L
BUSY#L
CS#R
t
BLC
t
PS
t
BHC
A
ddress Match
A
ddress R
BUS
Y
#R
t
BLA
Left Address Valid Firs
t
t
PS
t
BH
A
I
/
OL
[
15:0
]
Mismatch
A
D
V
#L
A
ddress L
(Internal
)
t
AV DH
Valid Left Address
A
ddress R
BUS
Y
#L
t
BLA
t
PS
t
BHA
I
/
OL[15:0]
A
D
V
#L
A
ddress L
(
Internal
)
t
A
VDH
Data
A
ddress Match
t
A
VDH
Valid Address Valid Addres
s
Mismatch
Valid Address
Right Address Valid Firs
t

CYDMX128A16-65BVXIT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM MoBLADM DP,x16,128Kb 65 or 90ns access
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union