CYDMX256A16/CYDMX256B16
CYDMX128A16/CYDMX128B16
CYDMX064A16/CYDMX064B16
Document Number: 001-08090 Rev. *I Page 13 of 25
AD Mux Port Write Cycle
[26]
t
WC
Write cycle time 65 65 90 ns
t
SCS
CS# Low to write end 65 65 90 ns
t
AVD
ADV# Low pulse 15 15 20 ns
t
AVDS
Address setup to ADV# rising edge 15 15 20 ns
t
AVDH
Address hold from ADV# rising edge 3 3 5 ns
t
CSS
CS# setup to ADV# rising edge 7 7 10 ns
t
WRL
WE# pulse width 28 28 45 ns
t
BW
UB#/LB# Low to write end 28 28 45 ns
t
SD
Data setup to write end 20 20 30 ns
t
HD
Data hold from write end 0 0 0 ns
t
LZWE
WE# High to IO Low Z 0 0 0 ns
t
AVWE
ADV# High to WE# Low 0 0 0 ns
Standard Port Read Cycle
[27]
t
RC
Read cycle time 40 60 60 ns
t
AA
Address to data valid 40 60 60 ns
t
OHA
Output hold from address change 5 5 5 ns
t
ACS
CS# to data valid 40 60 60 ns
t
DOE
OE# Low to data valid 25 35 35 ns
t
LZOE
[28]
OE# Low to data Low Z 5 5 5 ns
t
HZOE
OE# High to data High Z 10 30 30 ns
t
LZCS
CS# Low to data Low Z 5 5 5 ns
t
HZCS
CS# High to data High Z 10 30 30 ns
t
LZBE
UB#/LB# Low to data Low Z 5 5 5 ns
t
HZBE
UB#/LB# High to data High Z 10 30 30 ns
t
ABE
UB#/LB# access time 40 60 60 ns
Standard SRAM Port Write Cycle
t
WC
Write cycle time 40 60 60 ns
t
SCS
CS# Low to Write End 30 50 50 ns
t
AW
Address valid to write end 30 50 50 ns
t
HA
Address hold from write end 0 0 0 ns
t
SA
Address setup to write start 0 0 0 ns
Switching Characteristics for V
CC
= 1.8 V (continued)
Over the Operating Range
[23]
(continued)
Parameter Description
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16
Unit
–65 –65 –90
Min Max Min Max Min Max
Notes
26. AD Mux port timing applies to left AD Mux port and right port configured to AD Mux port.
27. Standard SRAM port timing applies to right port configured to standard SRAM port.
28. This parameter is guaranteed by not tested.
CYDMX256A16/CYDMX256B16
CYDMX128A16/CYDMX128B16
CYDMX064A16/CYDMX064B16
Document Number: 001-08090 Rev. *I Page 14 of 25
t
WRL
Write pulse width 25 45 45 ns
t
SD
Data setup to write end 20 30 30 ns
t
HD
Data hold from write end 0 0 0 ns
t
HZWE
WE# Low to data High Z 15 25 25 ns
t
LZWE
WE# High to data Low Z 0 0 0 ns
Arbitration Timing
t
BLA
BUSY# Low from address match 30 50 50 ns
t
BHA
BUSY# High from address mismatch 30 50 50 ns
t
BLC
BUSY# Low from CS# Low 30 50 50 ns
t
BHC
BUSY# High from CS# High 30 50 50 ns
t
PS
[29]
Port setup from priority 5 5 5 ns
t
BDD
BUSY# High to data valid 30 50 50 ns
t
WDD
Write pulse to data delay 55 85 85 ns
t
DDD
Write data valid to read data valid 45 70 70 ns
Interrupt Timing
t
INS
INT# set time 35 55 55 ns
t
INR
INT# reset time 35 55 55 ns
Switching Characteristics for V
CC
= 1.8 V (continued)
Over the Operating Range
[23]
(continued)
Parameter Description
CYDMX256A16
CYDMX128A16
CYDMX256B16
CYDMX128B16
CYDMX064B16
CYDMX256A16
CYDMX128A16
CYDMX064A16
Unit
–65 –65 –90
Min Max Min Max Min Max
Note
29. Add 2 ns to this parameter if VCC and VDDIOR are < 1.8 V, and VDDIOL is > 2.5 V at temperature < 0 °C.
CYDMX256A16/CYDMX256B16
CYDMX128A16/CYDMX128B16
CYDMX064A16/CYDMX064B16
Document Number: 001-08090 Rev. *I Page 15 of 25
Switching Waveforms
Figure 3. ADM Port Read Cycle (Either Port Access, WE# High)
Figure 4. ADM Port Write Cycle (Either Port Access, WE# Controlled, OE# High)
Valid Address
I/O
[
15:0
]
A
DV#
OE
#
W
E#
CS
#
Valid Data
t
A
VD
t
A
VD
S
t
AVDH
t
CSS
t
A
VO
E
t
A
CC3
t
A
CC1
t
A
CC2
t
HZC
S
t
HZO
E
t
A
VDA
t
O
E
UB#, LB#
t
LZBE
t
DBE
t
HZB
E
A
ddr1<15..0>
I/O
[
15:0
]
A
DV#
OE
#
W
E#
CS
#
WData1<15..0>
t
A
VW
E
t
WRL
t
SD
t
HD
t
A
VD
t
A
VD
S
t
A
VDH
t
CSS
t
SC
S
UB#, LB#
t
B
W

CYDMX128A16-65BVXIT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
SRAM MoBLADM DP,x16,128Kb 65 or 90ns access
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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