LTC4257-1
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If a sudden increase in voltage appears on the input line,
this voltage step will be transferred through capacitor C1
and appear across the power MOSFET. The response of
the LTC4257-1 will depend on the magnitude of the
voltage step, the rise time of the step, the value of capacitor
C1 and the DC load. For fast rising inputs, the LTC4257-1
will attempt to quickly charge capacitor C1 using an
internal secondary current limit circuit. In this scenario,
the PSE current limit should provide the overall limit for
the circuit. For slower rising inputs, the 375mA current
limit in the LTC4257-1 will set the charge rate of capacitor
C1. In either case, the PWRGD signal may go inactive
briefly while the capacitor is charged up to the new line
voltage. In the design of a PD, it is necessary to determine
if a step in the input voltage will cause the PWRGD signal
to go inactive and how to respond to this event. In some
designs, the charge on C1 is sufficient to power the PD
through this event. In this case, it may be desirable to filter
the PWRGD signal so that intermittent power bad condi-
tions are ignored. Figure 10 demonstrates methods to
insert a lowpass filter on the power good interface.
For PD designs that use a large load capacitor and also
consume a lot of power, it is important to delay activation
of the PD circuitry with the PWRGD signal. If the PD cir-
cuitry is not disabled during the current-limited turn-on se-
quence, the PD circuitry will rob current intended for charg-
ing up the load capacitor and create a slow rising input,
possibly causing the LTC4257-1 to go into thermal shut-
down.
The PWRGD pin connects to an internal open-drain, 100V
transistor capable of sinking 1mA. Low impedance indi-
cates power is good. PWRGD is high impedance during
signature and classification probing and in the event of a
thermal overload.
During turn-off, PWRGD is deactivated when the input
voltage drops below 30V. In addition, PWRGD may go
active briefly at turn-on for fast rising input waveforms.
PWRGD is referenced to the V
IN
pin and when active will
be near the V
IN
potential. The PD DC/DC converter will
typically be referenced to V
OUT
and care must be taken to
ensure that the difference in potential of the PWRGD signal
does not cause any detrimental effects. Use of diode clamp
D6, as shown in Figure 10, will alleviate any problems.
Thermal Protection
The LTC4257-1 includes thermal overload protection in
order to provide full device functionality in a miniature
package while maintaining safe operating temperatures.
Several factors create the possibility for tremendous
power dissi
pation within the LTC4257-1. At turn on,
before the load capacitor has charged up, the instanta-
neous power dissipated by the LTC4257-1 can be 10W. As
the load capacitor charges up, the power dissipation in the
LTC4257-1 will decrease until it reaches a steady-state
value dependent on the DC load current. The size of the
load capacitor determines how fast the power dissipation
in the LTC4257-1 will subside. At room temperature, the
LTC4257-1 can handle load capacitors as large as 800µF
without going into thermal shutdown. With a large load
capacitor like this, the LTC4257-1 die temperature will
increase by about 50°C during a single turn-on sequence.
If for some reason power were removed from the part and
then quickly reapplied so that the LTC4257-1 has to
charge up the load capacitor again, the temperature
rise would be excessive if safety precautions were not
implemented.
The LTC4257-1 protects itself from thermal damage by
monitoring the die temperature. If the die temperature
exceeds the overtemperature trip point, the current is
reduced to zero and very little power is dissipated in the
part until it cools below the overtemperature set point.
Once the LTC4257-1 has charged up the load capacitor
and the PD is powered and running, there will be some
residual heating due to the DC load current of the PD
flowing through the internal MOSFET. In some applica-
tions, the LTC4257-1 power dissipation may be signifi-
cant and if dissipated in the S8 package, excessive pack-
age heating could occur. This problem can be solved with
the use of the DD package which has superior thermal
performance. The DD package includes an exposed pad
which should be soldered to an isolated heatsink on the
printed circuit board.
During classification, excessive heating of the LTC4257-1
can occur if the PSE violates the 75ms probing time limit.
To protect the LTC4257-1, thermal protection circuitry will
disable classification current if the die temperature exceeds
APPLICATIO S I FOR ATIO
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