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LTC4257CDD-1#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
LTC4257-1
4
42571fb
Signature Resistance
vs Input Voltage
Normalized UVLO Threshold
vs Temperature
TYPICAL PERFOR A CE CHARACTERISTICS
UW
V
OUT
Leakage Current Current Limit vs Input Voltage
Input Current vs Input Voltage
Input Current vs Input Voltage
25k Detection Range Input Current vs Input Voltage
INPUT VOLTAGE (V)
0
0
INPUT CURRENT (mA)
0.1
0.2
0.3
0.4
0.5
–2
–4 –6 –8
4357 G01
–10
T
A
= 25°C
INPUT VOLTAGE (V)
0
0
INPUT CURRENT (mA)
10
20
30
40
50
–10
–20 –30 –40
42571 G02
–50 –60
CLASS 4
CLASS 3
CLASS 2
CLASS 1
CLASS 0
T
A
= 25°C
INPUT VOLTAGE (V)
–12
9.0
INPUT CURRENT (mA)
9.5
10.5
11.0
11.5
–14
–16
42571 G03
10.0
–18
–20 –22
12.0
85°C
–40°C
CLASS 1 OPERATION
Input Current vs Input Voltage
INPUT VOLTAGE (V)
0
INPUT CURRENT (mA)
1
2
3
–45 –55
42571 G04
–60–40 –50
EXCLUDES ANY LOAD CURRENT
T
A
= 25°C
INPUT VOLTAGE (V)
–1
22
V1:
V2:
SIGNATURE RESISTANCE (kΩ)
23
25
26
27
–3
–5
42571 G05
24
–7
–9
–6 –10
–2 –4
–8
28
RESISTANCE =
DIODES: S1B
T
A
= 25°C
=
∆V
∆I
V2 – V1
I
2
– I
1
IEEE UPPER LIMIT
IEEE LOWER LIMIT
LTC4257-1 + 2 DIODES
LTC4257-1 ONLY
TEMPERATURE (°C)
–40
–2
NORMALIZED UVLO THRESHOLD (%)
–1
0
1
2
–20 0 20 40
42571 G06
60 80
APPLICABLE TO TURN-ON
AND TURN-0FF THRESHOLDS
Power Good Output Low Voltage
vs Current
CURRENT (mA)
0
V
PG_OUT
(V)
2
3
8
42571 G07
1
0
2
4
6
10
4
T
A
= 25°C
V
OUT
PIN VOLTAGE (V)
0
0
V
OUT
CURRENT (µA)
30
60
120
90
20 40
42571 G08
60
V
IN
= 0V
T
A
= 25°C
INPUT VOLTAGE (V)
–40
CURRENT LIMIT (mA)
200
–60
42571 G09
100
–45
–50
–55
400
300
85°C
85°C
–40°C
–40°C
HIGH CURRENT MODE
LOW CURRENT MODE
LTC4257-1
5
42571fb
NC (Pin 1): No Internal Connection.
R
CLASS
(Pin 2): Class Select Input. Used to set the current
value the LTC4257-1 maintains during classification. Con-
nect a resistor between R
CLASS
and V
IN
(see Table 2).
NC (Pin 3): No Internal Connection.
V
IN
(Pin 4): Power Input. Tie to system –48V through the
input diode bridge.
V
OUT
(Pin 5): Power Output. Supplies –48V to the PD load
through an internal power MOSFET that limits input cur-
rent. V
OUT
is high impedance until the input voltage rises
above the turn-on UVLO threshold. The output is then
current limited. See Applications Information.
PWRGD (Pin 6): Power Good Output, Open-Drain. Signals
to the PD load that the LTC4257-1 MOSFET is on and that
the PD’s DC/DC converter can start operation. Low imped-
ance indicates power is good. PWRGD is high impedance
during detection, classification and in the event of a
thermal overload. PWRGD is referenced to V
IN
.
SIGDISA (Pin 7): Signature Disable Input. Allows the PD
to command the LTC4257-1 to present an invalid signa-
ture resistance and to remain inactive. Connecting SIGDISA
to GND lowers the signature resistance to an invalid value
and disables all functions of the LTC4257-1. If left floating,
SIGDISA is internally pulled to V
IN
. If unused, tie SIGDISA
to V
IN
.
GND (Pin 8): Ground. Tied to system ground and power
return through the input diode bridge.
UU
U
PI FU CTIO S
BLOCK DIAGRA
W
42571 BD
V
IN
BOLD LINE INDICATES HIGH CURRENT PATH
V
OUT
–
+
8
54
NC
3
R
CLASS
2
NC
PWRGD
SIGDISA
GND
1
7
6
CONTROL
CIRCUITS
INPUT
CURRENT
LIMIT
POWER GOOD
CLASSIFICATION
CURRENT LOAD
1.237V
EN
375mA
140mA
SIGNATURE DISABLE
9k
16k
0.3Ω
–
+
EN
25k SIGNATURE
RESISTOR
LTC4257-1
6
42571fb
The LTC4257-1 is intended for use as the front end of a
Powered Device (PD) adhering to the IEEE 802.3af standard.
The LTC4257-1 includes a trimmed 25k signature resistor,
classification current source, and an input current limit cir-
cuit. With these functions integrated into the LTC4257-1,
the signature and power interface for a PD that meets all
the requirements of the IEEE 802.3af specification can be
built with a minimum of external components.
The LTC4257-1 has been specifically designed to interface
with legacy PoE PSEs which do not meet the inrush
current requirement of the IEEE 802.3af specification. By
setting the initial inrush current limit to a low level, a PD
using the LTC4257-1 minimizes the current drawn from
the PSE during start-up. After powering up, the LTC4257-1
switches to the high level current limit, thereby allowing
the PD to consume up to 12.95 watts if an 802.3af PSE is
present. This low level current limit also allows the
LTC4257-1 to charge arbitrarily large load capacitors
without exceeding the inrush limits of the IEEE 802.3af
specification. This dual level current limit provides the
system designer with flexibility to design PDs which are
compatible with legacy PSEs while also being able to take
advantage of the higher power allocation available in an
IEEE 802.3af system.
Using an LTC4257-1 for the power and signature inter-
face functions of a PD provides several advantages. The
LTC4257-1 current limit circuit includes an onboard,
100V, 400mA power MOSFET with low leakage. This
onboard low leakage MOSFET avoids the possibility of
corrupting the 25k signature resistor while also saving
board space and cost. In addition, the inrush current limit
requirement of the IEEE 802.3af standard causes large
transient power dissipation in the PD. The LTC4257-1 is
designed to allow multiple turn-on sequences without
overheating the miniature 8-lead package. In the event of
excessive power cycling, the LTC4257-1 provides ther-
mal overload protection to keep the onboard power
MOSFET within its safe operating area.
Operation
The LTC4257-1 has several modes of operation depend-
ing on the applied input voltage as shown in Figure 1 and
DETECTION V1
CLASSIFICATION
UVLO
TURN-ON
UVLO
OFF
POWER
BAD
UVLO
OFF
UVLO
ON
UVLO
TURN-OFF
τ = R
LOAD
C1
PWRGD TRACKS
V
IN
DETECTION V2
10
TIME
20
30
V
IN
(V)
40
50
10
TIME
20
30
V
OUT
(V)
40
50
10
TIME
20
30
PWRGD (V)
40
50
I
CLASS
PD CURRENT
I
LIMIT
dV
dt
I
LIMIT
C1
=
POWER
BAD
POWER
GOOD
DETECTION I
1
CLASSIFICATION
I
CLASS
DETECTION I
2
LOAD, I
LOAD
CURRENT
LIMIT, I
LIMIT
42571 F01
I
CLASS
DEPENDENT ON R
CLASS
SELECTION
I
LIMIT
= 140mA (NOMINAL)
I
1
=
V1 – 2 DIODE DROPS
25kΩ
I
LOAD
=
V
IN
R
LOAD
I
2
=
V2 – 2 DIODE DROPS
25kΩ
GND
2
PSE
I
IN
LTC4257-1
8
6
5
R9 R
LOAD
R
CLASS
V
OUT
C1
GND
4
R
CLASS
PWRGD
V
OUT
V
IN
V
IN
Figure 1. Output Voltage, PWRGD and PD Current
as a Function of Input Voltage
APPLICATIO S I FOR ATIO
WUUU
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

LTC4257CDD-1#TRPBF

Mfr. #:
Buy LTC4257CDD-1#TRPBF
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN IEEE 802.3af PD Pwr over E Int Cntr w/ 2
Lifecycle:
New from this manufacturer.
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