74AUP1T57 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 9 of 20
NXP Semiconductors
74AUP1T57
Low-power configurable gate with voltage-level translator
[1] All typical values are measured at nominal V
CC
.
[2] t
pd
is the same as t
PLH
and t
PHL
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
V
CC
2
f
i
N+(C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of the outputs.
V
CC
= 3.0 V to 3.6 V; V
I
= 2.3 V to 2.7 V
t
pd
propagation delay A, B, C to Y; see Figure 12
[2]
C
L
= 5 pF 1.6 2.8 4.2 0.5 5.3 5.9 ns
C
L
= 10 pF 2.0 3.4 4.9 1.0 6.1 6.8 ns
C
L
= 15 pF 2.3 3.9 5.5 1.0 6.8 7.5 ns
C
L
= 30 pF 3.1 5.0 6.9 1.5 8.5 9.4 ns
V
CC
= 3.0 V to 3.6 V; V
I
= 3.0 V to 3.6 V
t
pd
propagation delay A, B, C to Y; see Figure 12
[2]
C
L
= 5 pF 1.3 2.8 4.2 0.5 4.7 5.2 ns
C
L
= 10 pF 1.7 3.3 4.9 1.0 5.7 6.3 ns
C
L
= 15 pF 2.0 3.8 5.5 1.0 6.2 6.9 ns
C
L
= 30 pF 2.8 4.9 7.0 1.5 7.8 8.6 ns
T
amb
= 25 C
C
PD
power dissipation
capacitance
f
i
= 1 MHz; V
I
= GND to V
CC
[3]
V
CC
= 2.3 V to 2.7 V - 3.6 - - - - pF
V
CC
= 3.0 V to 3.6 V - 4.3 - - - - pF
Table 9. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions 25 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max
(85 C)
Max
(125 C)
