74AUP1T57 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 3 of 20
NXP Semiconductors
74AUP1T57
Low-power configurable gate with voltage-level translator
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level.
Fig 2. Pin configuration SOT363 Fig 3. Pin configuration SOT886 Fig 4. Pin configuration SOT891,
SOT1115 and SOT1202
74AUP1T57
BC
GND
AY
001aah472
1
2
3
6
V
CC
5
4
74AUP1T57
GND
001aah471
B
A
V
CC
C
Y
Transparent top view
2
3
1
5
4
6
74AUP1T57
GND
001aah473
B
A
V
CC
C
Y
Transparent top view
2
3
1
5
4
6
Table 3. Pin description
Symbol Pin Description
B 1 data input
GND 2 ground (0 V)
A 3 data input
Y 4 data output
V
CC
5 supply voltage
C 6 data input
Table 4. Function table
[1]
Input Output
C B A Y
LLLH
LLHL
LHLH
LHHL
HLLL
HLHL
HHLH
HHHH
74AUP1T57 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 4 of 20
NXP Semiconductors
74AUP1T57
Low-power configurable gate with voltage-level translator
7.1 Logic configurations
Table 5. Function selection table
Logic function Figure
2-input AND see Figure 5
2-input AND with both inputs inverted see Figure 8
2-input NAND with inverted input see Figure 6 and 7
2-input OR with inverted input see Figure 6 and 7
2-input NOR see Figure 8
2-input NOR with both inputs inverted see Figure 5
2-input XNOR see Figure 9
Inverter see Figure 10
Buffer see Figure 11
Fig 5. 2-input AND gate or 2-input NOR gate with
both inputs inverted
Fig 6. 2-input NAND gate with input B inverted or
2-input OR gate with inverted C input
001aab584
B
B6
Y
C1
52
43Y
Y
C
B
C
V
CC
001aab585
B
B6
Y
C1
52
43Y
Y
C
B
C
V
CC
Fig 7. 2-input NAND gate with input C inverted or
2-input OR gate with inverted A input
Fig 8. 2-input NOR gate or 2-input AND gate with
both inputs inverted
001aab586
A
A
6
Y
C1
52
43Y
Y
C
A
C
V
CC
001aab587
A
6C1
52
43Y
V
CC
A
Y
C
Y
A
C
Fig 9. 2-input XNOR gate Fig 10. Inverter
001aab588
B6C1
52
43Y
V
CC
Y
B
C
74AUP1T57 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 5 of 20
NXP Semiconductors
74AUP1T57
Low-power configurable gate with voltage-level translator
8. Limiting values
[1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For SC-88 package: above 87.5 C the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of P
tot
derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Fig 11. Buffer
001aab590
B
B6
Y
1
52
43Y
V
CC
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +4.6 V
I
IK
input clamping current V
I
<0V 50 - mA
V
I
input voltage
[1]
0.5 +4.6 V
I
OK
output clamping current V
O
<0V 50 - mA
V
O
output voltage Active mode and Power-down mode
[1]
0.5 +4.6 V
I
O
output current V
O
=0 VtoV
CC
- 20 mA
I
CC
supply current - 50 mA
I
GND
ground current 50 - mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation T
amb
= 40 C to +125 C
[2]
- 250 mW
Table 7. Recommended operating conditions
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 2.3 3.6 V
V
I
input voltage 0 3.6 V
V
O
output voltage Active mode 0 V
CC
V
Power-down mode; V
CC
=0V 0 3.6 V
T
amb
ambient temperature 40 +125 C

74AUP1T57GF,132

Mfr. #:
Manufacturer:
Nexperia
Description:
Translation - Voltage Levels 3V 1G LPOW CONF
Lifecycle:
New from this manufacturer.
Delivery:
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