DATA SHEET
ICS813N252AKI-04 REVISION A MAY 24, 2011 1 ©2011 Integrated Device Technology, Inc.
VCXO Jitter Attenuator &
FemtoClock
®
NG Multiplier
ICS813N252I-04
General Description
The ICS813N252I-04 is a PLL based synchronous multiplier that is
optimized for PDH or SONET to Ethernet clock jitter attenuation and
frequency translation. The device contains two internal frequency
multiplication stages that are cascaded in series. The first stage is a
VCXO PLL that is optimized to provide reference clock jitter
attenuation. The second stage is a FemtoClock
®
NG frequency
multiplier that provides the low jitter, high frequency Ethernet output
clock that easily meets Gigabit and 10 Gigabit Ethernet jitter
requirements. Pre-divider and output divider multiplication ratios are
selected using device selection control pins. The multiplication ratios
are optimized to support most common clock rates used in PDH,
SONET and Ethernet applications. The VCXO requires the use of an
external, inexpensive pullable crystal. The VCXO uses external
passive loop filter components which allows configuration of the PLL
loop bandwidth and damping characteristics. The device is
packaged in a space-saving 32-VFQFN package and supports
industrial temperature range.
Features
Fourth generation FemtoClock® Next Generation (NG)
technology
One LVPECL output pair and one LVDS output pair
Each output supports independent frequency selection at 25MHz,
125MHz, 156.25MHz and 312.5MHz
Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, SSTL, HCSL
Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
Attenuates the phase jitter of the input clock by using a low-cost
pullable fundamental mode VCXO crystal
VCXO PLL bandwidth can be optimized for jitter attenuation and
reference tracking using external loop filter connection
FemtoClock NG frequency multiplier provides low jitter, high
frequency output
Absolute pull range: 100ppm
FemtoClock NG VCO frequency: 625MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz – 20MHz): 0.3ps (typical)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
LF1
LF0
ISET
V
EE
CLK_SEL
V
CC
RESERVED
V
EE
VEE
nQB
QB
V
CCO
nQA
QA
V
EE
ODASEL_0
PDSEL_2
PDSEL_1
PDSEL_0
V
CC
VCCA
ODBSEL_1
ODBSEL_0
ODASEL_1
XTAL_IN
XTAL_OU
T
CLK0
nCLK0
V
CC
CLK1
nCLK1
V
CCX
Pin Assignment
ICS813N252I-04
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
ICS813N252AKI-04 REVISION A MAY 24, 2011 2 ©2011 Integrated Device Technology, Inc.
ICS813N252I-04 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
NG MULTIPLIER
Block Diagram
Charge
Pump
VCXO
Phase
Detector
Output Divider
00 = 25
(default)
01 = 5
10 = 4
11 = 2
Output Divider
00 = 25
(default)
01 = 5
10 = 4
11 = 2
VCXO Feedback Divider
÷3125
VCXO Input
Pre-Divider
VCXO Jitter Attenuation PLL
XTAL_IN
XTAL_OUT
LF1
LF0
ISET
Loop
Filter
ODASEL_[1:0]
CLK0
PDSEL_[2:0]
nCLK0
0
1
25MHz
2
2
QB
nQB
ODBSEL_[1:0]
000 = 1
001 = 193
010 = 256
011 = 2430
100 = 3125
101 = 9720
110 = 15625
CLK1
nCLK1
CLK_SEL
Pulldown
Pulldown
Pulldown
Pullup
PU/PD
PU/PD
QA
nQA
111 = 19440
(default)
Pulldown
Pulldown
LVDS
LVPECL
FemtoClock NG
PLL
625MHz
3
ICS813N252AKI-04 REVISION A MAY 24, 2011 3 ©2011 Integrated Device Technology, Inc.
ICS813N252I-04 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
NG MULTIPLIER
Table 1. Pin Descriptions
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2 LF1, LF0
Analog
Input/Output
Loop filter connection node pins. LF0 is the output. LF1 is the input.
3 ISET
Analog
Input/Output
Charge pump current setting pin.
4, 8, 18,
24
V
EE
Power Negative supply pins.
5 CLK_SEL Input Pulldown
Input clock select. When HIGH selects CLK1/nCLK1. When LOW, selects
CLK0/nCLK0. LVCMOS / LVTTL interface levels.
6, 12, 27 V
CC
Power Core supply pins.
7 RESERVED Reserved Reserve pin. Do not connect.
9,
10,
11
PDSEL_2,
PDSEL_1,
PDSEL_0
Input Pullup
Pre-divider select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
13 V
CCA
Power Analog supply pin.
14,
15
ODBSEL_1,
ODBSEL_0
Input Pulldown
Frequency select pins for QB, nQB outputs. See Table 3B.
LVCMOS/LVTTL interface levels.
16,
17
ODASEL_1,
ODASEL_0
Input Pulldown
Frequency select pins for QA, nQA outputs. See Table 3B.
LVCMOS/LVTTL interface levels.
19, 20 QA, nQA Output Differential clock outputs. LVDS interface levels.
21 V
CCO
Power Output supply pin.
22, 23 QB, nQB Output Differential clock outputs. LVPECL interface levels.
25 nCLK1 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
26 CLK1 Input Pulldown Non-inverting differential clock input.
28 nCLK0 Input
Pullup/
Pulldown
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
29 CLK0 Input Pulldown Non-inverting differential clock input.
30,
31
XTAL_OUT,
XTAL_IN
Input Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
32 V
CCX
Power Power supply pin for the XTAL oscillator regulator.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k

813N252AKI-04LF

Mfr. #:
Manufacturer:
Description:
IC VCXO ATTENUATOR/MULT 32VFQFPN
Lifecycle:
New from this manufacturer.
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