ICS813N252AKI-04 REVISION A MAY 24, 2011 7 ©2011 Integrated Device Technology, Inc.
ICS813N252I-04 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
NG MULTIPLIER
Table 4C. Differential DC Characteristics, V
CC
= V
CCO
= V
CCX
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined at the crosspoint.
Table 4D. LVPECL DC Characteristics, V
CC
= V
CCO
= V
CCX
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
NOTE 1: Outputs terminated with 50 to V
CCO
– 2V. See Parameter Measurement Information section,
3.3V Output Load Test Circuit.
Table 4E. LVDS DC Characteristics, V
CC
= V
CCO
= V
CCX
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
CLK0, nCLK0,
CLK1, nCLK1
V
CC
= V
IN
= 3.465V 150 µA
I
IL
Input Low Current
CLK0, CLK1 V
CC
= 3.465V, V
IN
= 0V -10 µA
nCLK0, nCLK1 V
CC
= 3.465V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V
V
CMR
Common Mode Input Voltage; NOTE 1, 2 V
EE
V
CC
– 0.85 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1 V
CCO
– 1.10 V
CCO
– 0.75 V
V
OL
Output Low Voltage; NOTE 1 V
CCO
– 2.0 V
CCO
– 1.60 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.6 1.0 V
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OD
Differential Output Voltage 247 454 mV
V
OD
V
OD
Magnitude Change 60 mV
V
OS
Offset Voltage 1.125 1.375 V
V
OS
V
OS
Magnitude Change 50 mV
ICS813N252AKI-04 REVISION A MAY 24, 2011 8 ©2011 Integrated Device Technology, Inc.
ICS813N252I-04 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
NG MULTIPLIER
AC Electrical Characteristics
Table 5. AC Characteristics, V
CC
= V
CCO
= V
CCX
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized with outputs at the same frequency using the loop filter components for the mid loop bandwidth.
Refer to VCXO-PLL Loop Bandwidth Selection Table.
NOTE 1: Refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage. Measured at the output differential cross points.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
IN
Input Frequency 25MHz crystal Frequency 0.008 155.52 MHz
f
OUT
Output Frequency 25 312.5 MHz
t
jit(Ø)
RMS Phase Jitter, (Random);
NOTE 1
f
OUT
= 125MHz, 156.25MHz, 312.5MHz,
25MHz crystal,
Integration Range: 12kHz – 20MHz
0.3 0.7 ps
t
jit(pk-pk) Peak-to-Peak Jitter
QA 1e -12BER 60 ps
QB 1e -12BER 25 ps
t
sk(o) Output Skew; NOTE 2, 3 75 ps
t
R
/ t
F
Output Rise/Fall Time
QA 20% to 80% 150 400 ps
QB 20% to 80% 150 500 ps
odc Output Duty Cycle 48 52 %
t
LOCK
PLL Lock Time 6s
ICS813N252AKI-04 REVISION A MAY 24, 2011 9 ©2011 Integrated Device Technology, Inc.
ICS813N252I-04 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
NG MULTIPLIER
Typical Phase Noise
Noise Power dBc
Hz
Offset Frequency (Hz)

813N252AKI-04LF

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IC VCXO ATTENUATOR/MULT 32VFQFPN
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