ICS813N252AKI-04 REVISION A MAY 24, 2011 16 ©2011 Integrated Device Technology, Inc.
ICS813N252I-04 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
NG MULTIPLIER
Schematic Example
Figure 7 shows an example of ICS813N252I-04 application
schematic. In this example, the device is operated at V
CC
= V
CCX
=
V
CCO
= 3.3V. The decoupling capacitors should be located as close
as possible to the power pin. The input is driven by a 3.3V LVPECL
driver. Two examples of LVPECL and one example of LVDS
terminations are shown in this schematic. An optional 3-pole filter can
also be used for additional spur reduction. It is recommended that the
loop filter components be laid out for the 3-pole option. This will also
allow the 2-pole filter to be used.
Figure 7. ICS813N252I-04 Schematic Example
To Logic
Input
pins
C8
0.1u
Zo = 50
+
-
3-pole loop filter example - (optional)
X1
VCC
R2
125
VCC
VCC
CLK0
R9
TBD k
Zo = 50
Zo = 50
nQB
R11
133
R3
84
Logic Control Input Examples
LF
U1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
LF1
LF0
ISET
VEE
CLK_SEL
VCC
RESERVED
VEE
PDSEL_2
PDSEL_1
PDSEL_0
VCC
VCCA
ODBSEL_1
ODBSEL_0
ODASEL_1
ODASEL_0
VEE
QA
nQA
VCCO
QB
nQB
VEE
VCCX
XTAL_IN
XTAL_OUT
CLK0
nCLK0
VCC
CLK1
nCLK1
R7
84
nCLK1
Rs
470k
Zo = 50 Ohm
RU2
Not Install
+
-
VCC
Zo = 50 Ohm
C11
10u
LVPECL Driv er
R6
125
PDSEL_0
R16
50
R8
85
2-pole loop filter for Mid Bandwidth setting
R13
82.5
Cs
0.2uF
VCC
Cs
0.2uF
ODASEL_1
LVPECL Driv er
nCLK0
R10
133
LF
R1
125
Rs
470k
VCCX
nQA
R5
125
XTAL_OUT
VCC Zo = 50 Ohm
C2
TU N E
XTAL_IN
C9
0.1u
R17
50
C7
0.1u
QA
VCC
Set Logic
Input to
'0'
R14
82.5
R20
100
Set Logic
Input to
'1'
LVPECL
Termination
nCLK0
ODASEL_0
C10
0.01u
VCC
To Logic
Input
pins
LVDS
Termination
VCC
PDSEL_1
QB
ODBSEL_1
VCCA
RD2
1K
ODBSEL_0
+
-
3.3V
CLK_SEL
Cp
0.002uF
LVPECL
Optional
Y-Termination
R18
50
Zo = 50
C5
0.01u
R15
2.21K
VCC = VCCX = VCCO= 3.3V
R12 10
VCCO
CLK0
C4
0.1u
Zo = 50 Ohm
VCC
Cp
0.002uF
PDSEL_2
C6
10u
LF
C3
TBD pF
R19
10
RU1
1K
C1
TU N E
RD1
Not Install
CLK1
LF
R4
84
ICS813N252AKI-04 REVISION A MAY 24, 2011 17 ©2011 Integrated Device Technology, Inc.
ICS813N252I-04 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
NG MULTIPLIER
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality operation
of the VCXO-PLL. In choosing a crystal, special precaution must be
taken with the package and load capacitance (C
L
). In addition,
frequency, accuracy and temperature range must also be
considered. Since the pulling range of a crystal also varies with the
package, it is recommended that a metal-canned package like HC49
be used. Generally, a metal-canned package has a larger pulling
range than a surface mounted device (SMD). For crystal selection
information, refer to the
VCXO Crystal Selection Application Note.
The crystal’s load capacitance C
L
characteristic determines its
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance, IC
package lead capacitance, internal varactor capacitance and any
installed tuning capacitors (C
TUNE
).
If the crystal C
L
is greater than the total external capacitance, the
VCXO will oscillate at a higher frequency than the crystal
specification. If the crystal C
L
is lower than the total external
capacitance, the VCXO will oscillate at a lower frequency than the
crystal specification. In either case, the absolute tuning range is
reduced. The correct value of C
L
is dependant on the characteristics
of the VCXO. The recommended C
L
in the Crystal Parameter Table
balances the tuning range by centering the tuning curve.
The frequency of oscillation in
the third overtone mode is not
necessarily at exactly three
times the fundamental
frequency. The mechanical
properties of the quartz element
dictate the position of the
overtones relative to the
fundamental. The oscillator
circuit may excite both the
fundamental and overtone
modes simultaneously. This will
cause a nonlinearity in the tuning
curve. This potential problem is
why VCXO crystals are required to be tested for absence of any
activity inside a ±200 ppm window at three times the fundamental
frequency. Refer to F
L_3OVT
and F
L_3OVT_spurs
in the crystal
Characteristics table.
The crystal and external loop filter components should be kept as
close as possible to the device. Loop filter and crystal traces should
be kept short and separated from each other. Other signal traces
should be kept separate and not run underneath the device, loop
filter or crystal components.
VCXO Characteristics Table
VCXO-PLL Loop Bandwidth Selection Table
Crystal Characteristics
LF0
LF1
ISET
XTAL_IN
XTAL_OUT
R
S
C
S
C
P
R
SET
C
TUNE
C
TUNE
25MHz
Symbol Parameter Typical Units
k
VCXO
VCXO Gain 4.4 kHz/V
C
V_LOW
Low Varactor Capacitance 8 pF
C
V_HIGH
High Varactor Capacitance 16 pF
Bandwidth Crystal Frequency (MHz) M R
S
(k)C
S
(µF) C
P
(µF) R
SET
(k)
8Hz (Low) 25 3125 680 0.20 0.002 22
20Hz (Mid) 25 3125 470 0.20 0.002 5
75Hz (High) 25 3125 680 0.02 0.0003 2.2
Symbol Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
f
N
Frequency 25 MHz
f
T
Frequency Tolerance ±20 ppm
f
S
Frequency Stability ±20 ppm
Operating Temperature Range -40 85
0
C
C
L
Load Capacitance 10 pF
C
O
Shunt Capacitance 4 pF
C
O
/ C
1
Pullability Ratio 220 240
F
L_3OVT
3
rd
Overtone F
L
200 ppm
F
L_3OVT_spurs
3
rd
Overtone F
L
Spurs 200 ppm
ESR Equivalent Series Resistance 20
Drive Level 1mW
Aging @ 25
0
C ±3 per year ppm
ICS813N252AKI-04 REVISION A MAY 24, 2011 18 ©2011 Integrated Device Technology, Inc.
ICS813N252I-04 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
NG MULTIPLIER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS813N252I-04.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS813N252I-04 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core_LVDS)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 225mA = 779.625mW
Power (outputs)
MAX
= 31.55mW/Loaded Output pair
Total Power_
MAX
(3.3V, with all outputs switching) = 779.625mW + 31.55mW = 811.175mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θ
JA
* Pd_total + T
A
Tj = Junction Temperature
θ
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 37°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.811W * 37°C/W = 115°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θ
JA
for 32 Lead VFQFN, Forced Convection
θ
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29°C/W

813N252AKI-04LF

Mfr. #:
Manufacturer:
Description:
IC VCXO ATTENUATOR/MULT 32VFQFPN
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New from this manufacturer.
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