OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

813N252AKI-04LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
ICS813N252AKI-04 REVISION A MAY 24, 2011 19 ©2011 Integrated Device Technology, Inc.
ICS813N252I-04 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
NG MULTIPLIER
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in
Figure 8.
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of
V
CCO
– 2V.
• For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
– 0.75V
(V
CCO_MAX
– V
OH_MAX
) = 0.75V
• For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
– 1.6V
(V
CCO_MAX
– V
OL_MAX
) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
– 2V))/R
L
] * (V
CCO_MAX
– V
OH_MAX
) = [(2V – (V
CCO_MAX
– V
OH_MAX
))/R
L
] * (V
CCO_MAX
– V
OH_MAX
) =
[(2V – 0.75V)/50Ω] * 0.75V = 18.75mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
– 2V))/R
L
] * (V
CCO_MAX
– V
OL_MAX
) = [(2V – (V
CCO_MAX
– V
OL_MAX
))/R
L]
* (V
CCO_MAX
– V
OL_MAX
) =
[(2V – 1.6V)/50Ω] * 1.6V = 12.80mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 31.55mW
V
OUT
V
CCO
V
CCO
- 2V
Q1
RL
50
Ω
ICS813N252AKI-04 REVISION A MAY 24, 2011 20 ©2011 Integrated Device Technology, Inc.
ICS813N252I-04 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
NG MULTIPLIER
Reliability Information
Table 7. θ
JA
vs. Air Flow Table for a 32 Lead VFQFN
Transistor Count
The transistor count for ICS813N252I-04 is: 22,280
θ
JA
vs. Air Flow
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 37.0°C/W 32.4°C/W 29°C/W
ICS813N252AKI-04 REVISION A MAY 24, 2011 21 ©2011 Integrated Device Technology, Inc.
ICS813N252I-04 Data Sheet VCXO JITTER ATTENUATOR & FEMTOCLOCK
®
NG MULTIPLIER
Package Outline and Package Dimensions
Package Outline - K Suffix for 32 Lead VFQFN
Table 8. Package Dimensions
Reference Document: JEDEC Publication 95, MO-220
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 8.
To p View
Index Area
D
Cham fer 4x
0.6 x 0.6 max
OPTIONAL
Anvil
Singula tion
A
0. 08 C
C
A3
A1
S eating Plan e
E2
E2
2
L
(N
-1)x e
(R ef.)
(Ref.)
N & N
Even
N
e
D2
2
D2
(Ref.)
N & N
Odd
1
2
e
2
(Ty p.)
If N & N
are Even
(N -1)x e
(Re f.)
b
Th er mal
Ba se
N
OR
Anvil
Singulation
or
Sawn
Singulation
N-1N
CHAMFER
1
2
N-1
1
2
N
RADIUS
4
4
Bottom View w/Type C IDBottom View w/Type A ID
There are 2 methods of indicating pin 1 corner at the back of the VFQFN package are:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type C: Mouse bite on the paddle (near pin 1)
JEDEC Variation: VHHD-2/-4
All Dimensions in Millimeters
Symbol Minimum Nominal Maximum
N 32
A 0.80 1.00
A1 00.05
A3 0.25 Ref.
b 0.18 0.25 0.30
N
D
& N
E
8
D & E 5.00 Basic
D2 & E2 3.0 3.3
e 0.50 Basic
L 0.30 0.40 0.50
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

813N252AKI-04LF

Mfr. #:
Buy 813N252AKI-04LF
Manufacturer:
Description:
IC VCXO ATTENUATOR/MULT 32VFQFPN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet