74LVC823A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 4 — 8 April 2013 5 of 21
NXP Semiconductors
74LVC823A
9-bit D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration SO24 and (T)SSOP24 Fig 6. Pin configuration DHVQFN24
823
OE
V
CC
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
D8 Q8
MR CE
GND CP
001aaa845
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23
001aaa846
823
Transparent top view
CE
D8
MR
Q8
D7 Q7
D6 Q6
D5 Q5
D4 Q4
D3 Q3
D2 Q2
D1 Q1
D0 Q0
GND
CP
OE
V
CC
11 14
10 15
9 16
8 17
7 18
6 19
5 20
4 21
3 22
2 23
12
13
1
24
terminal 1
index area
GND
(1)
Table 2. Pin description
Pin Name Description
OE
1 output enable input (active LOW)
MR
11 master reset input (active LOW)
D[0:8] 2, 3, 4, 5, 6, 7, 8, 9, 10 data input
Q[0:8] 23, 22, 21, 20, 19, 18, 17, 16, 15 3-state flip-flop output
CP 13 clock input (LOW to HIGH; edge-triggered)
CE
14 clock enable input (active LOW)
GND 12 ground (0 V)
V
CC
24 supply voltage
