LTC3026
7
3026ff
pin FuncTions
IN (Pins 1, 2): Input Supply Voltage. Output load current
is supplied directly from IN. The IN pin should be locally
bypassed to ground if the LTC3026 is more than a few
inches away from another source of bulk capacitance.
In general, the output impedance of a battery rises with
frequency, so it is usually advisable to include an input
bypass capacitor when supplying IN from a battery. A
capacitor in the range of 0.1µF to 4.7µF is usually sufficient.
GND (Pin 3, Exposed Pad Pin 11): Ground and Heat Sink.
Connect the exposed pad to the PCB ground plane or large
pad for optimum thermal performance.
SW (Pin 4): Boost Switching Pin. This is the boost converter
switching pin. A 4.7µH to 40µH inductor able to handle a
peak current of 150mA is connected from this pin to V
IN
.
The boost converter can be disabled by floating this pin.
This allows the use of an external boosted supply from
a second LTC3026 or other source. See Operating with
Boost Converter Disabled section for more information.
BST (Pin 5): Boost Output Voltage Pin. With boost con-
verter enabled bypass the BST pin with a ≥4.7µF low ESR
ceramic capacitor to GND (C
BST
). BST does not load V
IN
when in shutdown, but is diode connected to IN through
the external inductor, thus, will not go to ground with V
IN
present. Users should not present any loads to the BST
pin (with boost enabled) until PG signals that regulation
has been achieved. When providing an external BST volt-
age (i.e. boost converter disabled) a 1µF low ESR ceramic
capacitor can be used.
SHDN (Pin 6): Shutdown Input Pin, Active Low. This pin
is used to put the LTC3026 into shutdown. The SHDN pin
current is typically less than 10nA. The SHDN pin cannot
be left floating and must be tied to a valid logic level (such
as IN) if not used.
PG (Pin 7): Power Good Pin. When PG is high impedance
OUT is in regulation, and low impedance when OUT is in
shutdown or out of regulation.
ADJ (Pin 8): Output Adjust Pin. This is the input to the error
amplifier. It has a typical bias current of 0.1nA flowing into
the pin. The ADJ pin reference voltage is 0.4V referenced
to ground. The output voltage range is 0.4V to 2.6V and is
typically set by connecting ADJ to a resistor divider from
OUT to GND. See Figure 2.
OUT (Pins 9, 10): Regulated Output Voltage. The OUT pins
supply power to the load. A minimum output capacitance
of 5µF is required to ensure stability. Larger output capaci-
tors may be required for applications with large transient
loads to limit peak voltage transients. See the Applica-
tions Information section for more information on output
capacitance.
LTC3026
8
3026ff
+
+
+
+
SWITCHING
LOGIC
EN
SHDN
0.4V
REFERENCE
BOOST
CONVERTER
6
7
4 5
8
UVLO
1,2
SW
IN
OUT
BST
SHDN
ADJ
PG
9,10
0.372V
3026 BD
GND
3,11
+
OVERSHOOT DETECT
V
OFF
block DiagraM
LTC3026
9
3026ff
The LTC3026 is a VLDO (very low dropout) linear regulator
which operates from input voltages as low as 1.14V. The
LDO uses an internal NMOS transistor as the pass device
in a source-follower configuration. The BST pin provides
the higher supply necessary for the LDO circuitry while the
output current comes directly from the IN input for high
efficiency regulation. The BST pin can either be supplied
off-chip by an external 5V source or it can be generated
through the internal boost converter of the LTC3026.
Boost Converter Operation
For applications where an external 5V supply is not avail-
able, the LTC3026 contains an internal boost converter to
produce the necessary 5V supply for the LDO. The boost
converter utilizes Burst Mode
®
operation to achieve high
efficiency for the relatively low current levels needed for
the LDO circuitry. The boost converter requires only a
small chip inductor between the IN and SW pins and a
small 4.7µF capacitor at BST.
The operation of the boost converter is described as fol-
lows. During the first half of the switching cycle, an internal
NMOS switch between SW and GND turns on, ramping
the inductor current. A peak comparator senses when the
inductor current reaches 100mA, at which point the NMOS
is turned off and an internal PMOS between SW and BST
turns on, transferring the inductor current to the BST pin.
The PMOS switch continues to deliver power to BST until
the inductor current approaches zero, at which point the
PMOS turns off and the NMOS turns back on, repeating
the switching cycle.
A burst comparator with hysteresis monitors the voltage
on the BST pin. When BST is above the upper threshold
of the comparator, no switching occurs. When BST falls
below the comparators lower threshold, switching com-
mences and the BST pin gets charged. The upper and lower
thresholds of the burst comparator are set to maintain a 5V
supply at BST with approximately 40mV to 50mV of ripple.
Care must be taken not to short the BST pin to GND, since
the body diode of the internal PMOS transistor connects
the BST and SW pins. Shorting BST to GND with an induc-
tor connected between IN and SW can ramp the inductor
current to destructive levels, potentially destroying the
inductor and/or the part.
Operating with Boost Converter Disabled
The LTC3026 has an option to disable the internal boost
converter. With the boost converter disabled, the LTC3026
becomes a bootstrapped device and the BST pin must be
driven by an external 5V supply, or driven by the BST pin
of a second LTC3026 with the boost converter enabled. The
recommended method for disabling the boost converter
is to simply float the SW pin. With the SW pin floating no
energy can be transferred to BST which effectively disables
the boost converter.
A single LTC3026 boost converter can be used to drive
multiple bootstrapped LTC3026s with the internal boost
converters disabled. Thus a single inductor can be used
to power two (or possibly more) functioning LTC3026s.
In cases where all LTC3026s have the same input supply
(IN) the internal boost converters of the bootstrapped
LTC3026s can be disabled by floating the SW pin. If the
LTC3026s are not all connected to the same input supply
then the internal boost converters of the bootstrapped
LTC3026s are disabled by floating the SW pin.
LDO Operation
An undervoltage lockout comparator (UVLO) senses the
BST pin voltage to ensure that the bias supply for the LDO
is greater than 4.2V before enabling the LDO. If BST is
below 4.2V, the UVLO shuts down the LDO, and OUT is
pulled to GND through the external divider.
operaTion

LTC3026EMSE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
LDO Voltage Regulators 1.5A VLDO in MSE
Lifecycle:
New from this manufacturer.
Delivery:
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