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AD9985ABSTZ-110

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
110 MSPS/140 MSPS Analog Interface for
Flat Panel Displays
AD9985
Rev. 0
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Specifications subject to change without notice. No license is granted by implication
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Tel: 781.329.4700
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Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
FEATURES
Automated clamping level adjustment
140 MSPS maximum conversion rate
300 MHz analog bandwidth
0.5 V to 1.0 V analog input range
500 ps p-p PLL clock jitter at 110 MSPS
3.3 V power supply
Full sync processing
Sync detect for hot plugging
Midscale clamping
Power-down mode
Low power: 500 mW typical
4:2:2 output format mode
APPLICATIONS
RGB graphics processing
LCD monitors and projectors
Plasma display panels
Scan converters
Microdisplays
Digital TV
FUNCTIONAL BLOCK DIAGRAM
R
AIN
R
OUTA
G
AIN
G
OUTA
B
AIN
B
OUTA
MIDSCV
SYNC
PROCESSING
AND CLOCK
GENERATION
DTACK
HSOUT
VSOUT
SOGOUT
REF
REF
BYPASS
SERIAL REGISTER AND
POWER MANAGEMENT
SCL
SDA
A0
SOGIN
FILT
C
LAMP
COAS
T
HSYNC
AD9985
CLAMP
8
A/D
CLAMP
8
A/D
CLAMP
8
A/D
04799-0-001
AUTO CLAMP
LEVEL ADJUST
AUTO CLAMP
LEVEL ADJUST
AUTO CLAMP
LEVEL ADJUST
Figure 1.
GENERAL DESCRIPTION
The AD9985 is a complete 8-bit, 140 MSPS, monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode rate
capability and full power analog bandwidth of 300 MHz
support resolutions up to SXGA (1280 × 1024 at 75 Hz).
The AD9985 includes a 140 MHz triple ADC with internal
1.25 V reference, a PLL, and programmable gain, offset, and
clamp control. The user provides only a 3.3 V power supply,
analog input, and Hsync and COAST signals. Three-state
CMOS outputs may be powered from 2.5 V to 3.3 V.
The AD9985’s on-chip PLL generates a pixel clock from the
Hsync input. Pixel clock output frequencies range from 12 MHz
to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS.
When the COAST signal is presented, the PLL maintains its
output frequency in the absence of Hsync. A sampling phase
adjustment is provided. Data, Hsync, and clock output phase
relationships are maintained. The AD9985 also offers full sync
processing for composite sync and sync-on-green applications.
A clamp signal is generated internally or may be provided by
the user through the CLAMP input pin. This interface is fully
programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9985 is
provided in a space-saving 80-lead LQFP surface-mount
plastic package and is specified over the –40°C to +85°C
temperature range.
AD9985* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DOCUMENTATION
Application Notes
• AN-745: Implementing the Auto-Offset Function on the
AD9985
Data Sheet
• AD9985: 110 MSPS/140 MSPS Analog Interface for Flat
Panel Displays Data Sheet
SOFTWARE AND SYSTEMS REQUIREMENTS
• AD988x Evaluation Tools Software Program
REFERENCE MATERIALS
Informational
• Advantiv™ Advanced TV Solutions
Technical Articles
• Analysis of Common Failures of HDMI CT
DESIGN RESOURCES
• AD9985 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
DISCUSSIONS
View all AD9985 EngineerZone Discussions.
SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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AD9985
Rev. 0 | Page 2 of 32
TABLE OF CONTENTS
Revision History ........................................................................... 2
Specifications..................................................................................... 3
Explanation of Test Levels........................................................... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Design Guide................................................................................... 11
General Description................................................................... 11
Digital Inputs .............................................................................. 11
Input Signal Handling................................................................ 11
Hsync, Vsync Inputs................................................................... 11
Serial Control Port ..................................................................... 11
Output Signal Handling............................................................. 11
Clamping ..................................................................................... 11
RGB Clamping........................................................................ 11
YUV Clamping ....................................................................... 12
Gain and Offset Control............................................................ 12
Auto Offset .............................................................................. 12
Sync-on-Green............................................................................ 13
Clock Generation ....................................................................... 13
Power Management.................................................................... 14
Timing.......................................................................................... 15
Hsync Timing ............................................................................. 15
Coast Timing............................................................................... 15
2-Wire Serial Register Map....................................................... 16
2-Wire Serial Control Register Detail Chip Identification... 19
PLL Divider Control .................................................................. 19
Clock Generator Control .......................................................... 19
Clamp Timing............................................................................. 20
Hsync Pulsewidth....................................................................... 20
Input Gain ................................................................................... 20
Input Offset ................................................................................. 20
Mode Control 1 .......................................................................... 21
2-Wire Serial Control Port........................................................ 26
Data Transfer via Serial Interface............................................. 26
Sync Slicer.................................................................................... 28
Sync Separator ............................................................................ 28
PCB Layout Recommendations ............................................... 29
Analog Interface Inputs............................................................. 29
Power Supply Bypassing............................................................ 29
PLL ............................................................................................... 30
Outputs (Both Data and Clocks).............................................. 30
Digital Inputs .............................................................................. 30
Voltage Reference ....................................................................... 30
Outline Dimensions....................................................................... 31
Ordering GuIde .......................................................................... 31
REVISION HISTORY
5/04—Revision 0: Initial Version
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

AD9985ABSTZ-110

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Manufacturer:
Analog Devices Inc.
Description:
Display Interface IC b-free8-bit analog intrfce; added filte
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