AD9985ABSTZ-110 Datasheet AD9985AKSTZ-110, AD9985ABSTZ-110, AD9985KSTZ-110 | P13-P15

AD9985

Rev. 0 | Page 12 of 32

input is present. The offset then remains in place when other

signal levels are processed, and the entire signal is shifted to

eliminate offset errors.

In most PC graphics systems, black is transmitted between

active video lines. With CRT displays, when the electron beam

has completed writing a horizontal line on the screen (at the

right side), the beam is deflected quickly to the left side of the

screen (called horizontal retrace), and a black signal is provided

to prevent the beam from disturbing the image.

In systems with embedded sync, a blacker-than-black signal

(Hsync) is produced briefly to signal the CRT that it is time to

begin a retrace. For obvious reasons, it is important to avoid

clamping on the tip of Hsync. Fortunately, there is virtually

always a period following Hsync, called the back porch, where a

good black reference is provided. This is the time when

clamping should be done.

The clamp timing can be established by simply exercising the

CLAMP pin at the appropriate time (with External Clamp = 1).

The polarity of this signal is set by the clamp polarity bit.

A simpler method of clamp timing employs the AD9985

internal clamp timing generator. The clamp placement register

is programmed with the number of pixel times that should pass

after the trailing edge of HSYNC before clamping starts. A

second register (clamp duration) sets the duration of the clamp.

These are both 8-bit values, providing considerable flexibility in

clamp generation. The clamp timing is referenced to the trailing

edge of Hsync because, though Hsync duration can vary widely,

the back porch (black reference) always follows Hsync. A good

starting point for establishing clamping is to set the clamp

placement to 09H (providing 9 pixel periods for the graphics

signal to stabilize after sync) and set the clamp duration to 14H

(giving the clamp 20 pixel periods to reestablish the black

reference).

Clamping is accomplished by placing an appropriate charge on

the external input coupling capacitor. The value of this capacitor

affects the performance of the clamp. If it is too small, there will

be a significant amplitude change during a horizontal line time

(between clamping intervals). If the capacitor is too large, then

it will take excessively long for the clamp to recover from a large

change in incoming signal offset. The recommended value

(47 nF) results in recovering from a step error of 100 mV to

within 1/2 LSB in 10 lines with a clamp duration of 20 pixel

periods on a 60 Hz SXGA signal.

YUV Clamping

YUV graphic signals are slightly different from RGB signals in

that the dc reference level (black level in RGB signals) can be at

the midpoint of the graphics signal rather than at the bottom.

For these signals, it can be necessary to clamp to the midscale

range of the A/D converter range (80H) rather than at the

bottom of the A/D converter range (00H).

Clamping to midscale rather than to ground can be accom-

plished by setting the clamp select bits in the serial bus register.

Each of the three converters has its own selection bit so that

they can be clamped to either midscale or ground inde-

pendently. These bits are located in Register 10H and are

Bits 0–2. The midscale reference voltage that each A/D

converter clamps to is provided on the MIDSCV pin (Pin 37).

This pin should be bypassed to ground with a 0.1 µF capacitor,

even if midscale clamping is not required.

GAIN

1.0

00H FFH

INPUT RANGE (V)

0.5

OFFSET = 00H

OFFSET = 3FH

OFFSET = 7FH

OFFSET = 00H

OFFSET = 7FH

OFFSET = 3FH

04799-0-004

Figure 4. Gain and Offset Control

GAIN AND OFFSET CONTROL

The AD9985 can accommodate input signals with inputs

ranging from 0.5 V to 1.0 V full scale. The full-scale range is set

in three 8-bit registers (Red Gain, Green Gain, and Blue Gain).

Note that increasing the gain setting results in an image with less

contrast.

The offset control shifts the entire input range, resulting in a

change in image brightness. Three 7-bit registers (Red Offset,

Green Offset, Blue Offset) provide independent settings for

each channel. The offset controls provide a ±63 LSB adjustment

range. This range is connected with the full-scale range, so if the

input range is doubled (from 0.5 V to 1.0 V) then the offset step

size is also doubled (from 2 mV per step to 4 mV per step).

Figure 4 illustrates the interaction of gain and offset controls.

The magnitude of an LSB in offset adjustment is proportional to

the full-scale range, so changing the full-scale range also

changes the offset. The change is minimal if the offset setting is

near midscale. When changing the offset, the full-scale range is

not affected, but the full-scale level is shifted by the same

amount as the zero-scale level.

Auto Offset

In addition to the manual offset adjustment mode (via

Registers 0Bh to 0Dh), the AD9985 also includes circuitry to

automatically calibrate the offset for each channel. By

monitoring the output of each ADC during the back porch of

the input signals, the AD9985 can self-adjust to eliminate any

AD9985

Rev. 0 | Page 13 of 32

offset errors in its own ADC channels as well as any offset

errors present on the incoming graphics or video signals.

To activate the auto-offset mode, set Register 1Dh, Bit 7 to 1.

Next, the target code registers (19h through 1Bh) must be

programmed. The values programmed into the target code

registers should be the output code desired from the AD9985

during the back porch reference time. For example, for RGB

signals, all three registers would normally be programmed to

code 1, while for YPbPr signals the green (Y) channel would

normally be programmed to code 1 and the blue and red

channels (Pb and Pr) would normally be set to 128. Any target

code value between 1 and 254 can be set, although the AD9985’s

offset range may not be able to reach every value. Intended

target code values range from (but are not limited to) 1 to 40

when ground clamping and 90 to 170 when midscale clamping.

The ability to program a target code for each channel gives

users a large degree of freedom and flexibility. While in most

cases all channels will be set to either 1 or 128, the flexibility to

select other values allows for the possibility of inserting

intentional skews between channels. It also allows for the ADC

range to be skewed so that voltages outside of the normal range

can be digitized. (For example, setting the target code to 40

would allow the sync tip, which is normally below black level, to

be digitized and evaluated.)

Lastly, when in auto offset mode, the manual offset registers

(0Bh to 0Dh) have new functionality. The values in these

registers are digitally added to the value of the ADC output. The

purpose of doing this is to match a benefit that is present with

manual offset adjustment. Adjusting these registers is an easy

way to make brightness adjustments. Although some signal

range is lost with this method, it has proven to be a very popular

function. In order to be able to increase and decrease brightness,

the values in these registers in this mode are signed twos

complement. The digital adder is used only when in auto offset

mode. Although it cannot be disabled, setting the offset registers

to all 0’s will effectively disable it by always adding 0.

SYNC-ON-GREEN

The Sync-on-Green input operates in two steps. First, it sets a

baseline clamp level off of the incoming video signal with a

negative peak detector. Second, it sets the sync trigger level to a

programmable level (typically 150 mV) above the negative peak.

The Sync-on-Green input must be ac-coupled to the Green

analog input through its own capacitor, as shown in Figure 5.

The value of the capacitor must be 1 nF ±20%. If Sync-on-

Green is not used, this connection is not required. Note that the

Sync-on-Green signal is always negative polarity.

AIN

SOG

47nF

1nF

04799-0-005

Figure 5. Typical Clamp Configuration

CLOCK GENERATION

A phase-locked loop (PLL) is employed to generate the pixel

clock. In this PLL, the Hsync input provides a reference

frequency. A voltage controlled oscillator (VCO) generates a

much higher pixel clock frequency. This pixel clock is divided

by the PLL divide value (Registers 01H and 02H) and phase

compared with the Hsync input. Any error is used to shift the

VCO frequency and maintain lock between the two signals.

The stability of this clock is a very important element in

providing the clearest and most stable image. During each pixel

time, there is a period during which the signal is slewing from

the old pixel amplitude and settling at its new value. Then there

is a time when the input voltage is stable, before the signal must

slew to a new value (Figure 6). The ratio of the slewing time to

the stable time is a function of the bandwidth of the graphics

DAC and the bandwidth of the transmission system (cable and

termination). It is also a function of the overall pixel rate.

Clearly, if the dynamic characteristics of the system remain

fixed, the slewing and settling time is likewise fixed. This time

must be subtracted from the total pixel period, leaving the stable

period. At higher pixel frequencies, the total cycle time is

shorter, and the stable pixel time becomes shorter as well.

PIXEL CLOCK INVALID SAMPLE TIMES

04799-0-006

Figure 6. Pixel Sampling Times

Any jitter in the clock reduces the precision with which the

sampling time can be determined, and must also be subtracted

from the stable pixel time.

Considerable care has been taken in the design of the AD9985’s

clock generation circuit to minimize jitter. As indicated in

Figure 7, the clock jitter of the AD9985 is less than 5% of the

total pixel time in all operating modes, making the reduction in

the valid sampling time due to jitter negligible.

AD9985

Rev. 0 | Page 14 of 32

FREQUENCY (MHz)

PIXEL CLOCK JITTER (p-p) (%)

10 20 30 40 50 60 70 80 90 100 110 120 130 140 150

04799-0-007

Figure 7. Pixel Clock Jitter vs. Frequency

The PLL characteristics are determined by the loop filter design,

by the PLL charge pump current, and by the VCO range setting.

The loop filter design is illustrated in Figure 8. Recommended

settings of VCO range and charge pump current for VESA

standard display modes are listed in Table 9.

0.0082µF

0.082µF

2.7kΩ

FILT

04799-0-008

Figure 8. PLL Loop Filter Detail

Four programmable registers are provided to optimize the

performance of the PLL:

1. The 12-Bit Divisor Register. The input Hsync frequencies

range from 15 kHz to 110 kHz. The PLL multiplies the

frequency of the Hsync signal, producing pixel clock

frequencies in the range of 12 MHz to 110 MHz. The

Divisor register controls the exact multiplication factor.

This register may be set to any value between 221 and 4095.

(The divide ratio that is actually used is the programmed

divide ratio plus one.)

2. The 2-Bit VCO Range Register. To improve the noise

performance of the AD9985, the VCO operating frequency

range is divided into three overlapping regions. The VCO

range register sets this operating range. Table 6 lists the

frequency ranges for the lowest and highest regions.

Table 6. VCO Frequency Ranges

Pixel Clock Range (MHz)

PV1 PV0 AD9985KSTZ AD9985BSTZ

0 0 12–32 12–30

0 1 32–64 30–60

1 0 64–110 60–110

1 1 110–140

3. The 3-Bit Charge Pump Current Register. This register

allows the current that drives the low-pass loop filter to be

varied. The possible current values are listed in Table 7.

Table 7. Charge Pump Current/Control Bits

Ip2 Ip1 Ip0 Current (µA)

0 0 0 50

0 0 1 100

0 1 0 150

0 1 1 250

1 0 0 350

1 0 1 500

1 1 0 750

1 1 1 1500

4. The 5-Bit Phase Adjust Register. The phase of the gen-

erated sampling clock may be shifted to locate an optimum

sampling point within a clock cycle. The phase adjust

Hsync signal with an identical phase shift is available

through the HSOUT pin.

The COAST pin is used to allow the PLL to continue to

run at the same frequency, in the absence of the incoming

Hsync signal or during disturbances in Hsync (such as

equalization pulses). This may be used during the vertical

sync period, or any other time that the Hsync signal is

unavailable. The polarity of the COAST signal may be set

through the coast polarity register. Also, the polarity of the

Hsync signal may be set through the Hsync polarity

Hsync and COAST polarity bits should be set to match the

respective polarities of the input signals.

POWER MANAGEMENT

The AD9985 uses the activity detect circuits, the active interface

bits in the serial bus, the active interface override bits, and the

power-down bit to determine the correct power state. There are

three power states—full-power, seek mode, and power-down.

Table 8 summarizes how the AD9985 determines what power

mode to be in and which circuitry is powered on/off in each of

these modes. The power-down command has priority over the

automatic circuitry.

Table 8. Power-Down Mode Descriptions

Mode

Inputs

Power-Down

Sync

Detect

Powered On or

Comments

Full-

Power

1 1 Everything

Seek

Mode

1 0

Serial Bus, Sync

Activity Detect, SOG,

Band Gap Reference

Power-

Down

0 X

Serial Bus, Sync

Activity Detect, SOG,

Band Gap Reference

Power-down is controlled via Bit 1 in serial bus Register 0FH.

Sync detect is determined by OR’ing Bits 7, 4, and 1 in serial bus

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33

AD9985ABSTZ-110

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Display Interface IC b-free8-bit analog intrfce; added filte

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AD9985ABSTZ-110

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