AD9985
Rev. 0 | Page 18 of 32
Hex
Address
Write and
Read or
Read Only Bits
Default
Value Register Name Function
*****0**
Bit 2 – Red Clamp Select. Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 37).
******0*
Bit 1 – Green Clamp Select. Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 37).
*******0
Bit 0 – Blue Clamp Select. Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 37).
11H R/W 7:0 00100000
Sync Separator
Threshold
Sync Separator Threshold. Sets how many internal 5 MHz clock periods
the sync separator will count to before toggling high or low. This
should be set to some number greater than the maximum Hsync or
equalization pulsewidth.
12H R/W 7:0 00000000 Pre-Coast
Pre-Coast. Sets the number of Hsync periods that Coast becomes
active prior to Vsync.
13H R/W 7:0 00000000 Post-Coast
Post-Coast. Sets the number of Hsync periods that Coast stays active
following Vsync.
14H RO 7:0 Sync Detect
Bit 7 – Hsync detect. It is set to Logic 1 if Hsync is present on the
analog interface; otherwise it is set to Logic 0.
Bit 6 – AHS: Active Hsync. This bit indicates which analog Hsync is
being used. (Logic 0 = Hsync Input Pin, Logic 1 = Hsync from Sync-on-
Green.)
Bit 5 – Input Hsync Polarity Detect. (Logic 0 = Active Low, Logic 1 =
Active High.)
Bit 4 – Vsync Detect. It is set to Logic 1 if Vsync is present on the analog
interface; otherwise it is set to Logic 0.
Bit 3 – AVS: Active Vsync. This bit indicates which analog Vsync is
being used. (Logic 0 = Vsync Input Pin, Logic 1 = Vsync from Sync
Separator.)
Bit 2 – Output Vsync Polarity Detect. (Logic 0 = Active Low, Logic 1 =
Active High.)
Bit 1 – Sync-on-Green Detect. It is set to Logic 1 if sync is present on
the Green video input; otherwise it is set to 0.
Bit 0 – Input Coast Polarity Detect. (Logic 0 = Active Low, Logic 1 =
Active High.)
15H
R/W
7:2 111111** Reserved
Bits [7:2] Reserved for future use. Must be written to 111111 for proper
operation.
1 ******1* Output Formats
Bit 1 – 4:2:2 Output Formatting Mode (Logic 0 = 4:2:2 mode, Logic 1=
4:4:4 mode)
0 *******1 Reserved Bit 0 – Must be set to 0 for proper operation.
16H
R/W
7:0 Test Register Reserved for future use.
17H RO 7:0 Test Register Reserved for future use.
18H RO 7:0 Test Register Reserved for future use.
19H
R/W
7:0 00000100 Red Target Code Target Code for Auto Offset Operation.
1AH
R/W
7:0 00000100
Green Target
Code
Target Code for Auto Offset Operation.
1BH
R/W
7:0 00000100
Blue Target
Code
Target Code for Auto Offset Operation.
1CH
R/W
7:0 00010001 Reserved Must be written to 11h for proper operation.
1DH
R/W
7 0*******
Auto Offset
Enable
Enables the auto offset circuitry.
6 *0****** Hold Auto Offset Holds the offset output of the auto offset at the current value.
5:2 **1001** Reserved Must be written to 9 for proper operation.
1:0 ******10 Update Mode Changes the update rate of the auto offset.
1EH
R/W
7:0 0000**** Test Register Must be set to default value.
*The AD9985 updates the PLL divide ratio only when the LSBs are written to (Register 02H).
AD9985
Rev. 0 | Page 19 of 32
2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP
IDENTIFICATION
00 7–0 Chip Revision
An 8-bit register that represents the silicon revision.
PLL DIVIDER CONTROL
01 7–0 PLL Divide Ratio MSBs
The 8 most significant bits of the 12-bit PLL divide
ratio PLLDIV. The operational divide ratio is
PLLDIV + 1.
The PLL derives a master clock from an incoming
Hsync signal. The master clock frequency is then
divided by an integer value, such that the output is
phase-locked to Hsync. This PLLDIV value
determines the number of pixel times (pixels plus
horizontal blanking overhead) per line. This is
typically 20% to 30% more than the number of active
pixels in the display.
The 12-bit value of the PLL divider supports divide
ratios from 2 to 4095. The higher the value loaded in
this register, the higher the resulting clock frequency
with respect to a fixed Hsync frequency.
VESA has established some standard timing
specifications that assist in determining the value for
PLLDIV as a function of horizontal and vertical
display resolution and frame rate (Table 9).
However, many computer systems do not conform
precisely to the recommendations, and these numbers
should be used only as a guide. The display system
manufacturer should provide automatic or manual
means for optimizing PLLDIV. An incorrectly set
PLLDIV will usually produce one or more vertical
noise bars on the display. The greater the error, the
greater the number of bars produced.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69H, PLLDIVL = DxH).
The AD9985 updates the full divide ratio only when
the LSBs are changed. Writing to the MSB by itself will
not trigger an update.
02 7–4 PLL Divide Ratio LSBs
The 4 least significant bits of the 12-bit PLL divide
ratio PLLDIV. The operational divide ratio is
PLLDIV + 1.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69H, PLLDIVL = DxH). The AD9985
updates the full divide ratio only when this register is
written to.
CLOCK GENERATOR CONTROL
03 7–6 VCO Range Select
Two bits that establish the operating range of the clock
generator.
VCORNGE must be set to correspond with the
desired operating frequency (incoming pixel rate).
The PLL gives the best jitter performance at high
frequencies. For this reason, to output low pixel rates
and still get good jitter performance, the PLL actually
operates at a higher frequency but then divides down
the clock rate afterwards.
Table 11 shows the pixel rates for each VCO range setting. The
PLL output divisor is automatically selected with the
VCO range setting.
Table 11. VCO Ranges
Pixel Clock Range (MHz)
PV1 PV0 AD9985KSTZ AD9985BSTZ
0 0 12–32 12–30
0 1 32–64 30–60
1 0 64–110 60–110
1 1 110–140
The power-up default value is 01.
03 5–3 CURRENT Charge Pump Current
Three bits that establish the current driving the loop
filter in the clock generator.
Table 12. Charge Pump Currents
CURRENT Current (µA)
000 50
001 100
010 150
011 250
100 350
101 500
110 750
111 1500
CURRENT must be set to correspond with the desired
operating frequency (incoming pixel rate).
The power-up default value is current = 001.
04 7–3 Clock Phase Adjust
A 5-bit value that adjusts the sampling phase in 32
steps across one pixel time. Each step represents an
11.25° shift in sampling phase.
The power-up default value is 16.
AD9985
Rev. 0 | Page 20 of 32
CLAMP TIMING
05 7–0 Clamp Placement
An 8-bit register that sets the position of the internally
generated clamp.
When Clamp Function (Register 0FH, Bit 7) = 0, a
clamp signal is generated internally, at a position
established by the clamp placement and for a duration
set by the clamp duration. Clamping is started (Clamp
Placement) pixel periods after the trailing edge of
Hsync. The clamp placement may be programmed to
any value between 1 and 255.
The clamp should be placed during a time that the
input signal presents a stable black-level reference,
usually the back porch period between Hsync and the
image.
When Clamp Function = 1, this register is ignored.
06 7–0 Clamp Duration
An 8-bit register that sets the duration of the
internally generated clamp.
For the best results, the clamp duration should be set
to include the majority of the black reference signal
time that follows the Hsync signal trailing edge.
Insufficient clamping time can produce brightness
changes at the top of the screen, and a slow recovery
from large changes in the average picture level (APL),
or brightness.
When Clamp Function = 1, this register is ignored.
HSYNC PULSEWIDTH
07 7–0 Hsync Output Pulsewidth
An 8-bit register that sets the duration of the Hsync
output pulse.
The leading edge of the Hsync output is triggered by
the internally generated, phase-adjusted PLL feedback
clock. The AD9985 then counts a number of pixel
clocks equal to the value in this register. This triggers
the trailing edge of the Hsync output, which is also
phase adjusted.
INPUT GAIN
08 7–0 Red Channel Gain Adjust
An 8-bit word that sets the gain of the Red channel.
The AD9985 can accommodate input signals with a
full-scale range of between 0.5 V and 1.0 V p-p.
Setting REDGAIN to 255 corresponds to a 1.0 V input
range. A REDGAIN of 0 establishes a 0.5 V input
range. Note that increasing REDGAIN results in the
picture having less contrast (the input signal uses
fewer of the available converter codes). See Figure 4.
09 7–0 Green Channel Gain Adjust
An 8-bit word that sets the gain of the Green channel.
See REDGAIN (08).
0A 7–0 Blue Channel Gain Adjust
An 8-bit word that sets the gain of the Blue channel.
See REDGAIN (08).
INPUT OFFSET
0B 7–1 Red Channel Offset Adjust
This and the following two offset registers have two
modes of operation. One mode is when the auto offset
function is turned off (manual mode) and the other is
when auto offset is turned on.
When in manual offset adjustment mode (auto offset
turned off) this register behaves exactly like the
AD9883A. It is a 7-bit offset binary word that sets the
dc offset of the Red channel. One LSB of offset
adjustment equals approximately one LSB change in
the ADC offset. Therefore, the absolute magnitude of
the offset adjustment scales as the gain of the channel
is changed. A nominal setting of 63 results in the
channel nominally clamping the back porch (during
the clamping interval) to Code 00. An offset setting of
127 results in the channel clamping to Code 64 of the
ADC. An offset setting of 0 clamps to Code –63 (off
the bottom of the range). Increasing the value of Red
Offset decreases the brightness of the channel.
When in auto offset mode, the value in this register is
digitally added to the red channel ADC output. The
purpose of doing this is to match a benefit that is
present with manual offset adjustment. Adjusting
these registers is an easy way to make brightness
adjustments. Although some signal range is lost with
this method, it has proven to be a very popular
function. In order to be able to increase and decrease
brightness, the values in these registers in this mode
are signed twos complement (as opposed to manual
mode where the values in this register are binary). The
digital adder is used only when in auto offset mode.
Although it cannot be disabled, setting this register to
all 0’s will effectively disable it by always adding 0.
0C 7–1 Green Channel Offset Adjust
This register works exactly like the Red Channel
Offset Adjust register (0Bh), except it is for the Green
Channel.
0D 7–1 Blue Channel Offset Adjust
This register works exactly like the Red Channel
Offset Adjust register (0Bh), except it is for the Blue
Channel.

AD9985ABSTZ-110

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Display Interface IC b-free8-bit analog intrfce; added filte
Lifecycle:
New from this manufacturer.
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