Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and
Data Recovery IC with Integrated Limiting Amp
Data Sheet
ADN2812
Rev. E
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FEATURES
Serial data input: 12.3 Mb/s to 2.7 Gb/s
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Quantizer sensitivity: 6 mV typical
Adjustable slice level: ±100 mV
Patented clock recovery architecture
Loss of signal (LOS) detect range: 3 mV to 15 mV
Independent slice level adjust and LOS detector
No reference clock required
Loss of lock indicator
I
2
C interface to access optional features
Single-supply operation: 3.3 V
Low power: 750 mW typical
5 mm × 5 mm 32-lead LFCSP
APPLICATIONS
SONET OC-1/OC-3/OC-12/OC-48 and all associated FEC rates
Fibre Channel, 2× Fibre Channel, GbE, HDTV
WDM transponders
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers
GENERAL DESCRIPTION
The ADN2812 provides the receiver functions of quantization,
signal level detect, and clock and data recovery for continuous
data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 auto-
matically locks to all data rates without the need for an external
reference clock or programming. All SONET jitter requirements
are met, including jitter transfer, jitter generation, and jitter
tolerance. All specifications are quoted for −40°C to +85°C
ambient temperature, unless otherwise noted.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power fiber
optic receiver.
The receiver front end, loss of signal (LOS) detector circuit
indicates when the input signal level has fallen below a user-
adjustable threshold. The LOS detect circuit has hysteresis to
prevent chatter at the output.
The ADN2812 is available in a compact 5 mm × 5 mm 32-lead
lead frame chip scale package (LFCSP).
FUNCTIONAL BLOCK DIAGRAM
2
04228-001
SLICEP/N
LOL
DATAOUTP/NLOSTHRADJ CLKOUTP/N
2
VCC VEECF1
CF2
PIN
NIN
VREF
QUANTIZER
VCO
PHASE
SHIFTER
PHASE
DETECT
FREQUENCY
DETECT
LOS
DETECT
DATA
RE-TIMING
LOOP
FILTER
LOOP
FILTER
REFCLKP/N
(OPTIONAL)
2
Figure 1.
ADN2812* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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EVALUATION KITS
ADN2812 Evaluation Board
DOCUMENTATION
Application Notes
AN-632: Provisionary Data Rates Using the AD9951 DDS as
an Agile Reference Clock for the ADN2812 Continuous-
Rate CDR
AN-657: ADN2812 Evaluation Board
AN-746: Supporting FDDI with the ADN2812
AN-757: Acquisition Times of the ADN2812
Data Sheet
ADN2812: Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock
and Data Recovery IC with Integrated Limiting Amp Data
Sheet
REFERENCE MATERIALS
Informational
Optical and High Speed Networking ICs
DESIGN RESOURCES
ADN2812 Material Declaration
PCN-PDN Information
Quality And Reliability
Symbols and Footprints
DISCUSSIONS
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SAMPLE AND BUY
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TECHNICAL SUPPORT
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ADN2812 Data Sheet
Rev. E | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Jitter Specifications ....................................................................... 4
Output and Timing Specifications ............................................. 5
Absolute Maximum Ratings ............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution .................................................................................. 6
Timing Characteristics ..................................................................... 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
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2
C Interface Timing and Internal Register Description ........... 10
Terminology .................................................................................... 12
Input Sensitivity and Input Overdrive ..................................... 12
Single-Ended vs. Differential .................................................... 12
LOS Response Time ................................................................... 12
Jitter Specifications ......................................................................... 13
Jitter Generation ......................................................................... 13
Jitter Transfer .............................................................................. 13
Jitter Tolerance ............................................................................ 13
Theory of Operation ...................................................................... 14
Functional Description .................................................................. 16
Frequency Acquisition ............................................................... 16
Limiting Amplifier ..................................................................... 16
Slice Adjust .................................................................................. 16
LOS Detector .............................................................................. 16
Lock Detector Operation .......................................................... 16
Harmonic Detector .................................................................... 17
Squelch Mode ............................................................................. 17
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2
C Interface ................................................................................ 18
Reference Clock (Optional) ...................................................... 18
Applications Information .............................................................. 21
PCB Design Guidelines ............................................................. 21
DC-Coupled Application .......................................................... 23
Coarse Data Rate Readback Look-Up Table ............................... 24
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
3/12Rev. D to Rev. E
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
5/10Rev. C to Rev. D
Changes to Figure 4, Table 5 ........................................................... 8
Changes to Figure 24 ...................................................................... 21
2/09Rev. B to Rev. C
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
6/07Rev. A to Rev. B
Changes to Table 1 ............................................................................ 3
Changes to Table 6 .......................................................................... 11
Changes to LTR Mode Description ............................................. 19
Changes to Ordering Guide .......................................................... 26
11/04Rev. 0 to Rev. A
Change to Specification .................................................................... 3
Updated Outline Dimensions ....................................................... 26
Changes to Using the Reference Clock to Lock onto Data
Section .............................................................................................. 19
3/04Revision 0: Initial Ve rsion

ADN2812ACPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Timers & Support Products Continuous Rate 12.3Mbs-2.7Gbs
Lifecycle:
New from this manufacturer.
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