ADN2812 Data Sheet
Rev. E | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04228-004
VCC 1
VCC 2
VREF 3
PIN 1
INDIC ATOR
TOP VIEW
(Not to Scale)
24 VCC
23 VEE
22 LOS
21 SDA
32 VCC
20 SCK
19 SADDR5
18 VCC
17 VEE
THRADJ 9
REFCLKP 10
REFCLKN 11
VCC 12
VEE 13
CF2 14
CF1 15
LOL 16
NIN 4
PIN5
SLICEP6
SLICEN7
VEE 8
31 VCC
30 VEE
29 DATAOUTP
28 DATAOUTN
27 SQUELCH
26 CLKOUTP
25 CLKOUTN
ADN2812*
* THERE IS AN EXPOSED PAD ON THE BOTTOM OF
THE PACKAGE THAT MUST BE CONNECTED TO GND.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
1 VCC AI Connect to VCC.
2 VCC P Power for Limamp, LOS.
3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor.
4 NIN AI Differential Data Input. CML.
5 PIN AI Differential Data Input. CML.
6 SLICEP AI Differential Slice Level Adjust Input.
7 SLICEN AI Differential Slice Level Adjust Input.
8 VEE P GND for Limamp, LOS.
9 THRADJ AI LOS Threshold Setting Resistor.
10 REFCLKP DI Differential REFCLK Input. 12.3 MHz to 200 MHz.
11 REFCLKN DI Differential REFCLK Input. 12.3 MHz to 200 MHz.
12 VCC P VCO Power.
13 VEE P VCO GND.
14 CF2 AO Frequency Loop Capacitor.
15 CF1 AO Frequency Loop Capacitor.
16 LOL DO Loss of Lock Indicator. LVTTL active high.
17 VEE P FLL Detector GND.
20 SCK DI I
C Clock Input.
21 SDA DI I
C Data Input.
22 LOS DO Loss of Signal Detect Output. Active high. LVTTL.
23 VEE P Output Buffer, I
C GND.
24 VCC P Output Buffer, I
C Power.
25 CLKOUTN DO Differential Recovered Clock Output. CML.
26 CLKOUTP DO Differential Recovered Clock Output. CML.
27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTLL.
28 DATAOUTN DO Differential Recovered Data Output. CML.
29 DATAOUTP DO Differential Recovered Data Output. CML.
30 VEE P Phase Detector, Phase Shifter GND.
31 VCC P Phase Detector, Phase Shifter Power.
32 VCC AI Connect to VCC.
Exposed Pad Pad P Connect to GND. Works as a heat sink.
1
P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
