ADN2812ACPZ Datasheet ADN2812ACPZ, ADN2812ACPZ-RL7, ADN2812ACPZ-RL | P16-P18

Data Sheet ADN2812

Rev. E | Page 15 of 28

At medium jitter frequencies, the gain and tuning range of the

VCO are not large enough to track input jitter. In this case, the

VCO control voltage becomes large and saturates, and the VCO

frequency dwells at one extreme of its tuning range or the other.

The size of the VCO tuning range, therefore, has only a small

effect on the jitter accommodation. The delay-locked loop

control voltage is now larger, so the phase shifter takes on the

burden of tracking the input jitter. The phase shifter range, in

UI, can be seen as a broad plateau on the jitter tolerance curve.

The phase shifter has a minimum range of 2 UI at all data rates.

The gain of the loop integrator is small for high jitter frequencies

so that larger phase differences are needed to make the loop

control voltage big enough to tune the range of the phase

shifter. Large phase errors at high jitter frequencies cannot be

tolerated. In this region, the gain of the integrator determines

the jitter accommodation. Because the gain of the loop integra-

tor declines linearly with frequency, jitter accommodation is

lower with higher jitter frequency. At the highest frequencies,

the loop gain is very small, and little tuning of the phase shifter

can be expected. In this case, jitter accommodation is determined

by the eye opening of the input data, the static phase error, and

the residual loop jitter generation. The jitter accommodation is

roughly 0.5 UI in this region. The corner frequency between the

declining slope and the flat region is the closed loop bandwidth

of the delay-locked loop, which is roughly 3 MHz at OC-48.

ADN2812 Data Sheet

Rev. E | Page 16 of 28

FUNCTIONAL DESCRIPTION

FREQUENCY ACQUISITION

The ADN2812 acquires frequency from the data over a range of

data frequencies from 12.3 Mb/s to 2.7 Gb/s. The lock detector

circuit compares the frequency of the VCO and the frequency

of the incoming data. When these frequencies differ by more

than 1000 ppm, LOL is asserted. This initiates a frequency

acquisition cycle. The VCO frequency is reset to the bottom

of its range, which is 12.3 MHz. The frequency detector then

compares this VCO frequency and the incoming data frequency

and increments the VCO frequency, if necessary. Initially, the

VCO frequency is incremented in large steps to aid fast acquisi-

tion. As the VCO frequency approaches the data frequency, the

step size is reduced until the VCO frequency is within 250 ppm

of the data frequency, at which point LOL is deasserted.

Once LOL is deasserted, the frequency-locked loop is turned

off. The PLL/DLL pulls in the VCO frequency the rest of the

way until the VCO frequency equals the data frequency.

The frequency loop requires a single external capacitor between

CF2 and CF1 (Pin 14 and Pin 15). A 0.47 µF ± 20%, X7R ceramic

chip capacitor with <10 nA leakage current is recommended.

Leakage current of the capacitor can be calculated by dividing

the maximum voltage across the 0.47 µF capacitor, ~3 V, by the

insulation resistance of the capacitor. The insulation resistance

of the 0.47 µF capacitor should be greater than 300 MΩ.

LIMITING AMPLIFIER

The limiting amplifier has differential inputs (PIN/NIN), which

are internally terminated with 50 Ω to an on-chip voltage reference

(VREF = 2.5 V typically). The inputs are typically ac‒coupled

externally, although dc coupling is possible as long as the input

common-mode voltage remains above 2.5 V (see Figure 28,

Figure 29, and Figure 30). Input offset is factory trimmed to

achieve better than 6 mV typical sensitivity with minimal drift.

The limiting amplifier can be driven differentially or single-

ended.

SLICE ADJUST

The quantizer slicing level can be offset by ±100 mV to mitigate

the effect of amplified spontaneous emission (ASE) noise or

duty cycle distortion by applying a differential voltage input of

up to ±0.95 V to the SLICEP/SLICEN inputs. If no adjustment

of the slice level is needed, SLICEP/SLICEN should be tied to

VEE. The gain of the slice adjustment is ~0.1 V/V.

LOS DETECTOR

The receiver front-end LOS detector circuit detects when the

input signal level has fallen below a user-adjustable threshold.

The threshold is set with a single external resistor from Pin 9

(THRADJ) to VEE. The LOS comparator trip point-vs.-resistor

value is illustrated in Figure 5. If the input level to the ADN2812

drops below the programmed LOS threshold, the output of the

LOS detector, LOS (Pin 22), is asserted to a Logic 1. The LOS

detector’s response time is ~500 ns by design but is dominated

by the RC time constant in ac-coupled applications. The LOS

pin defaults to active high. However, by setting Bit CTRLC[2]

to 1, the LOS pin is configured as active low.

Typically, 6 dB of electrical hysteresis is designed into the LOS

detector to prevent chatter on the LOS pin. This means that if

the input level drops below the programmed LOS threshold

causing the LOS pin to assert, the LOS pin is not deasserted

until the input level increases to 6 dB (2×) above the LOS

threshold (see Figure 19).

04228-019

HYSTERESIS

LOS OUTPUT

INPUT LEVEL

LOS THRESHOLD

INPUT VOLTAGE (V

DIFF

)

Figure 19. LOS Detector Hysteresis

The LOS detector and the SLICE level adjust can be used simul-

taneously on the ADN2812. This means that any offset added to

the input signal by the SLICE adjust pins does not affect the

LOS detector’s measurement of the absolute input level.

LOCK DETECTOR OPERATION

The lock detector on the ADN2812 has three modes of operation:

normal mode, REFCLK mode, and static LOL mode.

Normal Mode

In normal mode, the ADN2812 is a continuous rate CDR that

locks onto any data rate from 12.3 Mb/s to 2.7 Gb/s without the

use of a reference clock as an acquisition aid. In this mode, the

lock detector monitors the frequency difference between the

VCO and the input data frequency and deasserts the loss of

lock signal appearing on LOL (Pin 16) when the VCO is within

250 ppm of the data frequency. This enables the D/PLL, which

pulls the VCO frequency in the remaining amount and also

acquires phase lock. Once locked, if the input frequency error

exceeds 1000 ppm (0.1%), the loss of lock signal is reasserted

and control returns to the frequency loop, which begins a new

frequency acquisition starting at the lowest point in the VCO

operating range, 12.3 MHz. The LOL pin remains asserted until

the VCO locks onto a valid input data stream to within 250 ppm

frequency error. This hysteresis is shown in Figure 20.

Data Sheet ADN2812

Rev. E | Page 17 of 28

04228-020

LOL

0–250 250 1000 f

VCO

ERROR

(ppm)

–1000

Figure 20. Transfer Function of LOL

LOL Detector Operation Using a Reference Clock

(REFCLK Mode)

In REFCLK mode, a reference clock is used as an acquisition

aid to lock the ADN2812 VCO. Lock to reference mode is

enabled by setting CTRLA[0] to 1. The user also needs to

write to the CTRLA[7:6] and CTRLA[5:2] bits in order to set

the reference frequency range and the divide ratio of the data

rate with respect to the reference frequency. For more details,

see the Reference Clock (Optional) section. In this mode, the

lock detector monitors the difference in frequency between

the divided down VCO and the divided down reference clock.

The loss of lock signal, which appears on LOL (Pin 16), is deas-

serted when the VCO is within 250 ppm of the desired frequency.

This enables the D/PLL, which pulls the VCO frequency in the

remaining amount with respect to the input data and also acquires

phase lock. Once locked, if the input frequency error exceeds

1000 ppm (0.1%), the loss of lock signal is reasserted and

control returns to the frequency loop, which reacquires with

respect to the reference clock. The LOL pin remains asserted

until the VCO frequency is within 250 ppm of the desired

frequency. This hysteresis is shown in Figure 20.

Static LOL Mode

The ADN2812 implements a static LOL feature, which indicates

if a loss of lock condition has ever occurred and remains asserted,

even if the ADN2812 regains lock, until the static LOL bit is manu-

ally reset. The I

C register bit, MISC[4], is the static LOL bit. If

there is ever an occurrence of a loss of lock condition, this bit is

internally asserted to logic high. The MISC[4] bit remains high

even after the ADN2812 has reacquired lock to a new data rate.

This bit can be reset by writing a 1 followed by 0 to I

C Register

Bit CTRLB[6]. Once reset, the MISC[4] bit remains deasserted

until another loss of lock condition occurs.

Writing a 1 to I

C Register Bit CTRLB[7] causes the LOL pin

(Pin 16) to become a static LOL indicator. In this mode, the

LOL pin mirrors the contents of the MISC[4] bit and has the

functionality described in the previous paragraph. The CTRLB[7]

bit defaults to 0. In this mode, the LOL pin operates in the normal

operating mode, that is, it is asserted only when the ADN2812

is in acquisition mode and deasserts when the ADN2812 has

reacquired lock.

HARMONIC DETECTOR

The ADN2812 provides a harmonic detector, which detects

whether the input data has changed to a lower harmonic of the

data rate onto which the VCO is currently locked. For example,

if the input data instantaneously changes from OC-48, 2.488 Gb/s,

to an OC-12, 622.080 Mb/s bit stream, this could be perceived

as a valid OC-48 bit stream because the OC-12 data pattern is

exactly 4× slower than the OC-48 pattern. So, if the change in

data rate is instantaneous, a 101 pattern at OC-12 would be per-

ceived by the ADN2812 as a 111100001111 pattern at OC-48. If

the change to a lower harmonic is instantaneous, a typical CDR

could remain locked at the higher data rate.

The ADN2812 implements a harmonic detector that automati-

cally identifies whether the input data has switched to a lower

harmonic of the data rate onto which the VCO is currently

locked. When a harmonic is identified, the LOL pin is asserted

and a new frequency acquisition is initiated. The ADN2812

automatically locks onto the new data rate, and the LOL pin

is deasserted.

However, the harmonic detector does not detect higher har-

monics of the data rate. If the input data rate switches to a

higher harmonic of the data rate that the VCO is currently

locked onto, the VCO loses lock, the LOL pin is asserted,

and a new frequency acquisition is initiated. The ADN2812

automatically locks onto the new data rate.

The time to detect lock to harmonic is

16,384 × (T

/ρ)

where:

1/T

is the new data rate. For example, if the data rate is

switched from OC-48 to OC-12, then T

= 1/622 MHz.

ρ is the data transition density. Most coding schemes seek

to ensure that ρ = 0.5, for example, PRBS, 8B/10B.

When the ADN2812 is placed in lock to reference mode,

the harmonic detector is disabled.

SQUELCH MODE

Two squelch modes are available with the ADN2812.

Squelch DATAOUT and CLKOUT mode is selected

when CTRLC[1] = 0 (default mode). In this mode, when

the squelch input (Pin 27) is driven to a TTL high state,

both the clock and data outputs are set to the zero state to

suppress downstream processing. If the squelch function

is not required, Pin 27 should be tied to VEE.

Squelch DATAOUT or CLKOUT mode is selected when

CTRLC[1] is 1. In this mode, when the squelch input is

driven to a high state, the DATAOUT pins are squelched.

When the squelch input is driven to a low state, the CLKOUT

pins are squelched. This is especially useful in repeater appli-

cations, where the recovered clock may not be needed.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

ADN2812ACPZ

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Timers & Support Products Continuous Rate 12.3Mbs-2.7Gbs

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ADN2812ACPZ

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