Si5330
12 Rev. 1.0
14 CLK2A O Multi
Si5330A/B/C/K/L/M Differential Devices.
This is the positive side of the differential CLK2 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-Ended Devices.
This is one of the single-ended CLK2 outputs. Both
CLK2A and CLK2B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
15 VDDO2 VDD Supply
Output Clock Supply Voltage.
Supply voltage for CLK2A/B. Use a 0.1 µF bypass cap
as close as possible to this pin. If CLK2 is not used, this
pin must be tied to V
DD
(pin 7 and/or pin 24).
16 VDDO1 VDD Supply
Output Clock Supply Voltage.
Supply voltage for CLK1A,B. Use a 0.1 µF bypass cap
as close as possible to this pin. If CLK1 is not used, this
pin must be tied to V
DD
(pin 7 and/or pin 24).
17 CLK1B O Multi
Si5330A/B/C/K/L/M Differential Output Devices.
This is the negative side of the differential CLK1 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-Ended Output Devices.
This is one of the single-ended CLK1 outputs. Both
CLK1A and CLK1B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
18 CLK1A O Multi
Si5330A/B/C/K/L/M Differential Devices.
This is the positive side of the differential CLK1 output.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not in use.
Si5330F/G/H/J Single-Ended Devices.
This is one of the single-ended CLK1 outputs. Both
CLK1A and CLK1B single-ended outputs are in phase.
Refer to AN408 for interfacing and termination details.
Leave unconnected when not is use.
19 OEB I CMOS
Output Enable.
All outputs are enabled when the OEB pin is connected
to ground or below the V
IL
voltage for this pin. Connect-
ing the OEB pin to V
DD
or above the V
IH
level will dis-
able the outputs. Both V
IL
and V
IH
are specified in
Table 5. All outputs are forced to a logic “low” when dis-
abled. This pin is 3.3 V tolerant.
20 VDDO0 VDD Supply
Output Clock Supply Voltage.
Supply voltage for CLK0A,B. Use a 0.1 µF bypass cap
as close as possible to this pin. If CLK2 is not used, this
pin must be tied to V
DD
(pin 7 and/or pin 24).
Table 10. Si5330 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Type Description
