Si5330
Rev. 1.0 19
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Clarified documentation to reflect that Pin 19 is OEB
(OE Enable Low).
Updated Table 4, “Jitter Specifications” on page 7.
Revision 0.2 to Revision 0.3
Major editorial updates to improve clarity.
Updated “Additive Jitter” Specification Table.
Updated “Core Supply Current” Specification in
Table 2.
Removed the Low-Power LVPECL output options
from the ordering table in section 6.
Removed D/E ordering options.
Revision 0.3 to Revision 0.35
Typo of 150 ps on front page changed to 150 fs.
Updated PCB layout notes.
Added no ac coupling for LVDS outputs.
Changed input rise/fall time spec to 2 ns.
Revision 0.35 to Revision 1.0
Added maximum junction temperature specification
to Table 9 on page 8.
Added minimum and maximum duty cycle
specifications to Table 4 on page 5.
Updated Table 3, “Performance Characteristics,” on
page 5.
Added maximum propagation delay spec (4 ns).
Added test condition to t
LOS_B
in Table 3 on page 5.
Removed reference to frequency in Output-Output
Skew.
Updated Table 4, “Input and Output Clock
Characteristics,” on page 5.
Input voltage (max) changed “3.63” to “VDD”
Input voltage swing (max) change “3.63” with “—”.
Added Table 6, “Output Control Pins (LOS),” on
page 7.
Added tape and reel ordering information to "6.
Orderable Part Numbers and Device Functionality"
on page 14.
Added "9. Top Marking" on page 18.
