Si5330
Rev. 1.0 5
Table 3. Performance Characteristics
(V
DD
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85°C)
Parameter
Symbol Test Condition Min Typ Max Unit
CLKIN Loss of Signal Assert
Time
t
LOS
—2.6 5 µs
CLKIN Loss of Signal De-Assert
Time
t
LOS_B
After initial start-up time has
expired
0.01 0.2 1 µs
Input-to-Output Propagation
Delay
t
PROP
—2.54.0 ns
Output-Output Skew t
DSKEW
Outputs at same signal
format
——100 ps
POR to Output Clock Valid t
START
Start-up time for output
clocks
—— 2 ms
Table 4. Input and Output Clock Characteristics
(V
DD
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Units
Input Clock (AC Coupled Differential Input Clocks on Pin IN1/2)
Frequency
f
IN
5 — 710 MHz
Differential Voltage Swing
V
PP
710 MHz input 0.4 — 2.4 V
PP
Rise/Fall Time
t
R
/t
F
20%–80% — — 1.0 ns
Duty Cycle
DC < 1 ns tr/tf 40 50 60 %
Input Impedance
R
IN
10 — — k
Input Capacitance
C
IN
—3.5—pF
Input Clock (DC-Coupled Single-Ended Input Clock on Pin IN3)
Frequency
f
IN
CMOS 5 — 200 MHz
HSTL, SSTL 5 — 350 MHz
Input Voltage
V
I
–0.1 — VDD V
Input Voltage Swing
(CMOS Standard)
200MHz, Tr/Tf=1.3ns 0.8 — — Vpp
Rise/Fall Time
t
R
/t
F
20%–80% — — 4 ns
Duty Cycle
DC < 2 ns tr/tf 40 50 60 %
Input Capacitance
C
IN
—2—pF
Output Clocks (Differential)
Frequency
f
OUT
LVPECL, LVDS 5 — 710 MHz
HCSL 5 — 250 MHz
