Si5330
16 Rev. 1.0
7. Package Outline: 24-Lead QFN
Figure 4. 24-Lead Quad Flat No-Lead (QFN)
Table 12. Package Dimensions
Dimension Min Nom Max
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
D 4.00 BSC.
D2 2.35 2.50 2.65
e 0.50 BSC.
E 4.00 BSC.
E2 2.35 2.50 2.65
L 0.30 0.40 0.50
aaa 0.10
bbb 0.10
ccc 0.08
ddd 0.10
eee 0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Outline MO-220, variation VGGD-8.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
5. J-STD-020 MSL rating: MSL3.
6. Terminal base alloy: Cu.
7. Terminal plating/grid array material: Au/NiPd.
8. For more packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx.
Si5330
Rev. 1.0 17
8. Recommended PCB Layout
Table 13. PCB Land Pattern
Dimension Min Nom Max
P1 2.50 2.55 2.60
P2 2.50 2.55 2.60
X1 0.20 0.25 0.30
Y1 0.75
0.80 0.85
C1 3.90
C2 3.90
E0.50
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. Connect the center ground pad to a ground plane with no less than five vias to a ground plane that is no more than
20 mils below it. Via drill size should be no smaller than 10 mils. A longer distance to the ground plane is allowed if
more vias are used to keep the inductance from increasing.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is
to be 60 µm minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder
paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins.
9. A 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad.
Card Assembly
10. A No-Clean, Type-3 solder paste is recommended.
11. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
Si5330
18 Rev. 1.0
9. Top Marking
9.1. Si5330 Top Marking
9.2. Top Marking Explanation
Mark Method: Laser
Line 1 Marking: Device Part Number Si5330
Line 2 Marking: X = Frequency and configuration code.
xxxxx = Input and output format configu-
ration code.
See "6. Orderable Part Numbers and
Device Functionality" on page 14 for more
information.
Xxxxxx
Line 3 Marking: R = Product revision (A).
TTTTT = Manufacturing trace code.
RTTTTT
Line 4 Marking: Pin 1 indicator. Circle with 0.5 mm diameter;
left-justified
YY = Year.
WW = Work week.
Characters correspond to the year and
work week of package assembly.
YYWW
YYWW
RTTTTT
Xxxxxx
Si5330

SI5330F-A00215-GM

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Buffer Single-ended input, 2.5V CMOS output, 1:8 clock buffer, 5 - 200 MHz
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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