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953002CFLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
Integrated
Circuit
Systems, Inc.
ICS953002
0924—11/18/09
Pin Configuration
Recommended Application:
Chipset for P4 type processor with PCI-Express
Output Features:
• 2 - 0.7V current-mode differential CPU pairs
• 1 - 0.7V current-mode differential CPU/PCI-Express
selectable pair
• 6 - PCI, 33MHz
• 2 - REF, 14.318MHz
• 3 - 3V66, 66.66MHz
• 1 - 48MHz
• 1 - 24/48MHz
• 5 - PCI-Express 0.7V current mode differential pairs
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• 3V66 outputs cycle-cycle jitter < 250ps
• PCI outputs cycle-cycle jitter < 500ps
Programmable Timing Control Hub™ for Next Gen P4™ processor
Functionality
Features/Benefits:
• Programmable output frequency.
• Programmable asynchronous 3V66&PCI frequency.
• Programmable asynchronous PCI-Express frequency.
• Programmable output divider ratios.
• Programmable output skew.
• Programmable spread percentage for EMI control.
• Watchdog timer technology to reset system if system
malfunctions.
• Programmable watch dog safe frequency.
• Support I2C Index read/write and block read/write
operations.
• Uses external 14.318MHz reference input, external
crystal load caps are required for frequency tuning.
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
B0b4 B0b3 B0b2 B0b1 B0b0 PCI-EX AGP PCI CPU
FS4 FS3 FSL2 FSL1 FSL0 MHz MHz MHz MHz
00 0 0 0
100.00 66.66 33.33 266.66
00 0 0 1
100.00 66.66 33.33 133.33
00 0 1 0
100.00 66.66 33.33 200.00
00 0 1 1
100.00 66.66 33.33 166.66
00 1 0 0 N/AN/AN/AN/A
00 1 0 1
100.00 66.66 33.33 100.00
00 1 1 0
100.00 66.66 33.33 400.00
00 1 1 1
100.00 66.66 33.33 200.00
01 0 0 0
100.00 66.66 33.33 100.00
01 0 0 1
100.00 66.66 33.33 133.33
01 0 1 0
100.00 66.66 33.33 200.00
01 0 1 1
100.00 66.66 33.33 166.66
01 1 0 0
100.00 66.66 33.33 100.00
01 1 0 1
100.00 66.66 33.33 133.33
01 1 1 0
100.00 66.66 33.33 200.00
01 1 1 1
100.00 66.66 33.33 166.66
1 0 0 0 0 100.00 66.66 33.33 266.66
10 0 0 1
100.00 66.66 33.33 133.33
10 0 1 0
100.00 66.66 33.33 200.00
10 0 1 1
100.00 66.66 33.33 166.66
10 1 0 0
N/A N/A N/A N/A
10 1 0 1
100.00 66.66 33.33 100.00
10 1 1 0
100.00 66.66 33.33 400.00
10 1 1 1
100.00 66.66 33.33 200.00
11 0 0 0
100.00 66.66 33.33 266.66
11 0 0 1
100.00 66.66 33.33 133.33
11 0 1 0
100.00 66.66 33.33 200.00
11 0 1 1
100.00 66.66 33.33 166.66
11 1 0 0
N/A N/A N/A N/A
11 1 0 1
100.00 66.66 33.33 100.00
11 1 1 0
100.00 66.66 33.33 400.00
11 1 1 1
100.00 66.66 33.33 200.00
VDDA 1 56 GND
GND 2 55 IREF
VDDREF 3 54 CPUCLKT0
**FS
L
0/REF0 4 53 CPUCLKC0
FS
L
1/REF1 5 52 GNDCPU
X1 6 51 CPUCLKT1
X2 7 50 CPUCLKC1
GNDREF 8 49 VDDCPU
VttPWR_GD/PD# 9 48 SDATA
VDDPCI 10 47 CPUCLKT2_ITP/PCIEXT0
**FS
L
2/PCICLK0 11 46 CPUCLKC2_ITP/PCIEXC0
**FS3/~PCICLK1 12 45 VDDPCIEX
PCICLK2 13 44 PCIEXT1
PCICLK3 14 43 PCIEXC1
GNDPCI 15 42 PCIEXT2
VDDPCI 16 41 PCIEXC2
PCICLK4 17 40 GNDPCIEX
PCICLK5 18 39 VDDPCIEX
GNDPCI 19 38 PCIEXT3
*Turbo# 20 37 PCIEXC3
Reset# 21 36 PCIEXT4
VDD48 22 35 PCIEXC4
**Mode0/48MHz 23 34 PCIEXT5/CPU_STOP#*
*Sel24_48#/24_48MHz 24 33 PCIEXC5/PCI_PCIEX_STOP#*
GND48 25 32 GNDPCIEX
VDD3V66 26 31 SCLK
**ITP_EN/3V66_2 27 30 GND3V66
**FS4/3V66_1 28 29 3V66_0
~This output is default 2X drive strength.
ICS953002
56-Pin SSOP
*These inputs have 120K internal pull-up resistors to VDD.
**These inputs have 120K internal pull-down resistors to GND.
2
Integrated
Circuit
Systems, Inc.
ICS953002
0924—11/18/09
Pin Description
PIN # PIN NAME TYPE DESCRIPTION
1 VDDA PWR 3.3V power for the PLL core.
2 GND PWR Ground pin.
3 VDDREF PWR Ref, XTAL power supply, nominal 3.3V
4 **FSL0/REF0 I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / 14.318 MHz reference
5 FSL1/REF1 I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / 14.318 MHz reference
6 X1 IN Crystal input, Nominally 14.318MHz.
7 X2 OUT Crystal output, Nominally 14.318MHz
8 GNDREF PWR Ground pin for the REF outputs.
9 VttPWR_GD/PD# IN
This 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled. This is an active high
input. / Asynchronous active low input pin used to power down the device
into a low power state.
10 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V
11 **FSL2/PCICLK0 I/O
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. / 3.3V PCI clock output.
12 **FS3/~PCICLK1 I/O Frequency select latch input pin / 3.3V PCI clock output.
13 PCICLK2 OUT PCI clock output.
14 PCICLK3 OUT PCI clock output.
15 GNDPCI PWR Ground pin for the PCI outputs
16 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V
17 PCICLK4 OUT PCI clock output.
18 PCICLK5 OUT PCI clock output.
19 GNDPCI PWR Ground pin for the PCI outputs
20 *Turbo# IN
Real time input pin to change frequency to a pre-programmed under or over
clock entries located in the Rom table.
21 Reset# OUT
Real time system reset signal for frequency gear ratio change or watchdog
timer timeout. This signal is active low.
22 VDD48 PWR Power pin for the 48MHz output.3.3V
23 **Mode0/48MHz I/O
Function select pin, 1=Mobile Mode, 0=Desktop Mode / 48MHz clock output.
3.3V.
24 *Sel24_48#/24_48MHz I/O
Latched select input for 24/48MHz output / 24/48MHz clock output.
1=24MHz, 0 = 48MHz.
25 GND48 PWR Ground pin for the 48MHz outputs
26 VDD3V66 PWR Power pin for the 3.3V 66MHz clocks.
27 **ITP_EN/3V66_2 I/O
3.3V 66.66MHz clock output./
ITP_EN: latched input to select pin functionality
1 = CPU_2_ITP pair
0 = PCI-EX0 pair
28 **FS4/3V66_1 I/O Frequency select latch input pin / 66.66MHz clock output. 3.3V
3
Integrated
Circuit
Systems, Inc.
ICS953002
0924—11/18/09
Pin Description (Continued)
PIN # PIN NAME TYPE DESCRIPTION
29 3V66_0 OUT 3.3V 66.66MHz clock output
30 GND3V66 PWR Ground pin for the 3.3V 66MHz clocks
31 SCLK IN Clock pin of SMBus circuitry, 5V tolerant.
32 GNDPCIEX PWR Ground pin for the PCI-EX outputs
33
PCIEXC5/PCI_PCIEX_STO
P#*
OUT
Complement clock of differential PCI_Express pair. / Active low signal that
stops all PCI and PCIEX clocks besides the free running clocks
34 PCIEXT5/CPU_STOP#* OUT
True clock of differential PCI_Express pair./Stops all CPUCLK besides the
free running clocks
35 PCIEXC4 OUT Complement clock of differential PCI_Express pair.
36 PCIEXT4 OUT True clock of differential PCI_Express pair.
37 PCIEXC3 OUT Complement clock of differential PCI_Express pair.
38 PCIEXT3 OUT True clock of differential PCI_Express pair.
39 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V
40 GNDPCIEX PWR Ground pin for the PCI-EX outputs
41 PCIEXC2 OUT Complement clock of differential PCI_Express pair.
42 PCIEXT2 OUT True clock of differential PCI_Express pair.
43 PCIEXC1 OUT Complement clock of differential PCI_Express pair.
44 PCIEXT1 OUT True clock of differential PCI_Express pair.
45 VDDPCIEX PWR Power supply for PCI Express clocks, nominal 3.3V
46 CPUCLKC2_ITP/PCIEXC0 OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias./
Complement clock of differential PCIEX pair
47 CPUCLKT2_ITP/PCIEXT0 OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias. / True clock of
differential PCIEX pair
48 SDATA I/O Data pin for SMBus circuitry, 5V tolerant.
49 VDDCPU PWR Supply for CPU clocks, 3.3V nominal
50 CPUCLKC1 OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
51 CPUCLKT1 OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
52 GNDCPU PWR Ground pin for the CPU outputs
53 CPUCLKC0 OUT
Complementary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
54 CPUCLKT0 OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
55 IREF OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
56 GND PWR Ground pin.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

953002CFLF

Mfr. #:
Buy 953002CFLF
Manufacturer:
IDT
Description:
Clock Generators & Support Products PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
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