953002CFLF Datasheet 953002DFLFT, 953002CFLF, 953002CFLFT | P22-P24

22

Integrated

Circuit

Systems, Inc.

ICS953002

0924—11/18/09

I

2

C Table: Device Control Register

Bit 7

FS Source

Frequency H/W IIC

Select

RW 0

Bit 6

Reserved Reserved RW 1

Bit 5

ROD Reset On Demand RW 0

Bit 4

FS4 Freq/Div Sel Bit 4 RW latch

Bit 3

FS3 Freq/Div Sel Bit 3 RW latch

Bit 2

FSL2 Freq/Div Sel Bit 2 RW latch

Bit 1

FSL1 Freq/Div Sel Bit 1 RW latch

Bit 0

FSL0 Freq/Div Sel Bit 0 RW latch

I

2

C Table: Device Control Register

Bit 7

SS_EN1 PLL1 Spread Enable RW 1

Bit 6

SS_EN2 PLL2 Spread Enable RW 1

Bit 5

M/N Enable bit

M/N Programming

Enable bit

RW 0

Bit 4

CPUFS4 PLL1 VCO Sel b4 RW X

Bit 3

CPUFS3 PLL1 VCO Sel b3 RW X

Bit 2

CPUFS2 PLL1 VCO Sel b2 RW 0

Bit 1

CPUFS1 PLL1 VCO Sel b1 RW 0

Bit 0

CPUFS0 PLL1 VCO Sel b0 RW 0

B1b[4:3] = 00 is invalid

I

2

C Table: Output Control Register

Bit 7

REF0 Output Control RW 1

Bit 6

REF1 Output Control RW 1

Bit 5

PCICLK0 Output Control RW 1

Bit 4

PCICLK1 Output Control RW 1

Bit 3

PCICLK2 Output Control RW 1

Bit 2

PCICLK3 Output Control RW 1

Bit 1

PCICLK4 Output Control RW 1

Bit 0

PCICLK5 Output Control RW 1

I

2

C Table: Output Control Register

Bit 7

48MHz Output Control RW 1

Bit 6

24_48MHz Output Control RW 1

Bit 5

3V66_2 Output Control RW 1

Bit 4

3V66_1 Output Control RW 1

Bit 3

3V66_0 Output Control RW 1

Bit 2

- SEL24_48MHz Output Select RW Latch

Bit 1

ITP_EN Output Select RW Latch

Bit 0

Mode 0 Output Select RW Latch

Enable

Disable Enable

Enable

Disable

Disable Enable

Enable

CPU_STOP/PCI_P

CIEX_STOP

CPUCLKT/C2

48MHz 24MHz

-

PWD

-

Name Control Function Type 0

-

Byte 3

-

Name

1

Enable

Disable

Name Type

Control Function Type

PWD

1

01

Latch Inputs

OFF

Enable

-

PWD

-

Byte 1 Pin #

-

Pin #

-

Name

-

Byte 2 Pin #

-

TypeByte 0 Pin #

-

Control Function

IIC

ON

--

Disable Enable

See Table 1b: PLL2 AGP/PCI Frequency

Selection Table

OFF

0

Disable

PCIEXCLKT/C5

Disable

1

PCIEXCLKT/C0

Enable

Disable Enable

Enable

EnableDisable

Disable

Enable

See Table 1a: PLL1 Rom VCO

Frequency Selection Table

0

Enable

-

Enable

23

Integrated

Circuit

Systems, Inc.

ICS953002

0924—11/18/09

I

2

C Table: Out

p

ut Control Re

g

ister

Bit 7

PCIEXCLKT/C5 Output Control RW 1

Bit 6

PCIEXCLKT/C4 Output Control RW 1

Bit 5

PCIEXCLKT/C3 Output Control RW 1

Bit 4

PCIEXCLKT/C2 Output Control RW 1

Bit 3

PCIEXCLKT/C1 Output Control RW 1

Bit 2

CPUCLK2/PCIEX0 Output Control RW 1

Bit 1

CPUCLKT/C1 Output Control RW 1

Bit 0

CPUCLKT/C0 Output Control RW 1

I

2

C Table: Device Control Register

Bit 7

AGP/PCI PLL Cntrl AGP/PCI PLL Source RW 0

Bit 6

PCIEX PLL Cntrl PCIEX PLL Source RW 0

Bit 5

Reserved Reserved RW 1

Bit 4

Reserved Reserved RW 1

Bit 3

ASYNC1

RW 0

Bit 2

ASYNC0

RW 0

Bit 1

Reserved Reserved RW 1

Bit 0

Reserved Reserved RW 1

I

2

C Table: Reserved Register

Bit 7

Reserved Reserved RW 0

Bit 6

Reserved Reserved RW 0

Bit 5

Reserved Reserved RW 0

Bit 4

Reserved Reserved RW 0

Bit 3

Reserved Reserved RW 0

Bit 2

Reserved Reserved RW 0

Bit 1

Reserved Reserved RW 0

Bit 0

Reserved Reserved RW 0

I

2

C Table: Vendor ID Register

Bit 7

REVID3 Revision ID R 0

Bit 6

REVID2 Revision ID R 0

Bit 5

REVID1 Revision ID R 0

Bit 4

REVID0 Revision ID R 0

Bit 3

VID3 Vendor ID R 0

Bit 2

VID2 Vendor ID R 0

Bit 1

VID1 Vendor ID R 0

Bit 0

VID0 Vendor ID R 1

--

-

--

-

--

-

01 = 66.0/33.0

Enable

PLL1 PLL2

Disable

0

Enable

-

Byte 6 Pin #

-

Pin #

-

Name

-

Byte 4

-

Pin #

-

Name Control Function

Control Function

0

-

0001 = ICS

Type

TypeName

1PWD

1

01

Type

-

PWD

PWDByte 7

-

Name

-

Byte 5

-

Pin #

Control Function

3V66/PCI Async Freq

Prog bits

Disable

-

EnableDisable

Disable

-

00 = PLL1/2 10 = 75.4/37.7

PLL2

11 = 88.0/44.0

-

Disable

PLL1

-

0

-

Enable

Disable Enable

--

Enable

1

24

Integrated

Circuit

Systems, Inc.

ICS953002

0924—11/18/09

I

2

C Table: Byte Count Register

Bit 7

BC7 RW 0

Bit 6

BC6 RW 0

Bit 5

BC5 RW 0

Bit 4

BC4 RW 0

Bit 3

BC3 RW 1

Bit 2

BC2 RW 1

Bit 1

BC1 RW 1

Bit 0

BC0 RW 1

I

2

C Table: WD Time Control Register

Bit 7

WDEN Watchdog Enable RW 0

Bit 6

WDSEN

Watchdog Soft Reset

Enable

RW 0

Bit 5

WD Alarm Status WD Alarm Status R x

Bit 4

WD Soft Status WD Soft Reset Status R x

Bit 3

WDTCtrl

Watch Dog Time base

Control

RW 0

Bit 2

WD2 WD Timer Bit 2 RW 1

Bit 1

WD1 WD Timer Bit 1 RW 1

Bit 0

WD0 WD Timer Bit 0 RW 1

I

2

C Table: M/N Programming & WD Safe Frequency Control Register

Bit 7

Reserved Reserved RW 1

Bit 6

Reserved Reserved RW 1

Bit 5

WD Safe Freq

Source

WD Safe Freq Source RW 0

Bit 4

WD SF4 RW 0

Bit 3

WD SF3 RW 0

Bit 2

WD SF2 RW 0

Bit 1

WD SF1 RW 0

Bit 0

WD SF0 RW 0

I

2

C Table: PLL1 Frequency Control Register

Bit 7

N Div8 N Divider Prog bit 8 RW X

Bit 6

N Div9 N Divider Prog bit 9 RW X

Bit 5

M Div5 RW X

Bit 4

M Div4 RW X

Bit 3

M Div3 RW X

Bit 2

M Div2 RW X

Bit 1

M Div1 RW X

Bit 0

M Div0 RW X

NameByte 8 Pin #

-

Watch Dog Safe Freq

Programming bits

-

Byte 9 Pin # Name

-

PWD

M Divider

Programming bits

Type

PWD

PWDType

01

1

PWD

-

Byte Count

Programming b(7:0)

-

Type

-

Byte 10 Pin # Control FunctionName

-

Byte 11 Pin # Name

-

Control Function

0

Alarm

The decimal representation of M and N

Divier in Byte 11 and 12 will configure the

PLL1 VCO frequency. Default at power

up = latch-in or Byte 0 Rom table.

VCO Frequency = 14.318 x [NDiv(9:0)+8]

/ [MDiv(5:0)+2]

Disable Enable

1160ms Base

Writing to this register will configure how

many bytes will be read back, default is

0F = 15 bytes.

Writing to these bit will configure the safe

frequency as Byte0 bit (4:0).

-

B10b(4:0)

These bits represent X*290ms (or 1.16S)

the watchdog timer waits before it goes to

alarm mode. Default is 7 X 290ms = 2s.

290ms Base

01

Disable Enable

01

Normal

Latch Inputs

-

Alarm

953002CFLF

953002CFLF

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