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953002CFLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
28
Integrated
Circuit
Systems, Inc.
ICS953002
0924—11/18/09
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K)
resistor is used to provide both the solid CMOS programming
voltage needed during the power-up programming period and to
provide an insignificant load on the output clock during the
subsequent operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K W
8.2K W
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
29
Integrated
Circuit
Systems, Inc.
ICS953002
0924—11/18/09
Absolute Maximum Rating
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
3.3V Core Supply Voltage VDD_A
-
V
DD
+ 0.5V V
1
3.3V Logic Input Supply
Voltage
VDD_In
-
GND - 0.5 V
DD
+ 0.5V V
1
Storage Temperature Ts
-
-65 150
°
C
1
Ambient Operating Temp Tambient
-
070°C
1
Case Temperature Tcase
-
115 °C
1
Input ESD protection HBM ESD prot
-
2000 V
1
1
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER SYMBOL CONDITIONS* MIN TYP MAX UNITS Notes
Input High Voltage V
IH
3.3 V +/-5% 2 V
DD
+ 0.3 V 1
Input Low Voltage V
IL
3.3 V +/-5% V
SS
- 0.3 0.8 V 1
Input High Current I
IH
V
IN
= V
DD
-5 5 uA 1
I
IL1
V
IN
= 0 V; Inputs with no pull-up
resistors
-5 uA 1
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200 uA 1
Low Threshold Input-
High Voltage
V
IH_FS
3.3 V +/-5% 0.7 V
DD
+ 0.3 V 1
Low Threshold Input-
Low Voltage
V
IL_FS
3.3 V +/-5% V
SS
- 0.3 0.35 V 1
Operating Supply Current I
DD3.3OP
Full Active, C
L
= Full load; 350 mA 1
Operating Current I
DD3.3OP
all outputs driven 400 mA 1
all diff pairs driven 70 mA 1
all differential pairs tri-stated 12 mA 1
Input Frequency F
i
V
DD
= 3.3 V 14.31818 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs 5 pF 1
C
OUT
Output pin capacitance 6 pF 1
C
INX
X1 & X2 pins 5 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up or de-
assertion of PD# to 1st clock
1.8 ms 1
Modulation Frequency Triangular Modulation 30 33 kHz 1
Tdrive_PD#
CPU output enable after
PD# de-assertion
300 us 1
Tfall_Pd# PD# fall time of 5 ns 1
Trise_Pd# PD# rise time of 5 ns 1
SMBus Voltage V
DD
2.7 5.5 V 1
Low-level Output Voltage V
OL
@ I
PULLUP
0.4 V 1
Current sinking at
V
OL
= 0.4 V
I
PULLUP
4mA1
SCLK/SDATA
Clock/Data Rise Time
T
RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000 ns 1
SCLK/SDATA
Clock/Data Fall Time
T
FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300 ns 1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1
Guaranteed by design and characterization, not 100% tested in production.
2
Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
Input Low Current
Powerdown Current I
DD3.3PD
Input Capacitance
30
Integrated
Circuit
Systems, Inc.
ICS953002
0924—11/18/09
Electrical Characteristics - CPUCLKT/C -- 0.7V Current Mode Differential Pair
PARAMETER SYMBOL CONDITIONS* MIN TYP MAX UNITS NOTES
Current Source Output Impedance Zo
V
O
= V
x
3000
Ω
1
Voltage High VHigh 660 850 mV 1,3
Voltage Low VLow -150 150 mV 1,3
Max Voltage Vovs 1150 mV 1
Min Voltage Vuds -300 mV 1
Crossing Voltage (abs) Vx(abs) 250 550 mV 1
Crossing Voltage (var) d-Vx
Variation of crossing over all
ed
g
es
140 mV 1
Long Accuracy ppm see Tperiod min-max values -300 300 ppm 1,2
400MHz nominal 2.4993 2.5008 ns 2
400MHz spread 2.4993 2.5133 ns 2
333.33MHz nominal 2.9991 3.0009 ns 2
333.33MHz spread 2.9991 3.016 ns 2
266.66MHz nominal 3.7489 3.7511 ns 2
266.66MHz spread 3.7489 3.77 ns 2
200MHz nominal 4.9985 5.0015 ns 2
200MHz spread 4.9985 5.0266 ns 2
166.66MHz nominal 5.9982 6.0018 ns 2
166.66MHz spread 5.9982 6.0320 ns 2
133.33MHz nominal 7.4978 7.5023 ns 2
133.33MHz spread 7.4978 7.5400 ns 2
100.00MHz nominal 9.9970 10.0030 ns 2
100.00MHz spread 9.9970 10.0533 ns 2
400MHz nominal/spread 2.4143 ns 1,2
333.33MHz nominal/spread 2.9141 ns 1,2
266.66MHz nominal/spread 3.6639 ns 1,2
200MHz nominal/spread 4.8735 ns 1,2
166.66MHz nominal/spread 5.8732 ns 1,2
133.33MHz nominal/spread 7.3728 ns 1,2
100.00MHz nominal/spread 9.8720 ns 1,2
Rise Time
t
r
V
OL
= 0.175V, V
OH
= 0.525V
175 700 ps 1
Fall Time
t
f
V
OH
= 0.525V V
OL
= 0.175V
175 700 ps 1
Rise Time Variation
d-t
r
V
OL
= 0.175V, V
OH
= 0.525V
125 ps 1
Fall Time Variation
d-t
f
V
OH
= 0.525V V
OL
= 0.175V
125 ps 1
Duty Cycle
d
t3
Measurement from differential
wavefrom
45 55 % 1
Skew
t
sk3
CPU(1:0), V
T
= 50%
100 ps 1
Skew
t
sk4
CPU(1:0) to CPU2_ITP,
V
T
= 50%
150 ps 1
Jitter, Cycle to cycle
t
jcyc-cyc
Measurement from differential
wavefrom
(
CPU2_ITP
)
125 ps 1
Jitter, Cycle to cycle
t
jcyc-cyc
Measurement from differential
wavefrom
,
(
CPU
(
1:0
))
85 ps 1
*T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2
Ω
, R
P
=49.9
Ω, Ι
REF
= 475Ω
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475Ω (1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50Ω.
Statistical measurement on sin
le
ended signal
Measurement on single ended
signal using absolute value.
Average period Tperiod
Absolute min period
T
absmin
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953002CFLF

Mfr. #:
Buy 953002CFLF
Manufacturer:
IDT
Description:
Clock Generators & Support Products PC MAIN CLOCK
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