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72V3612L20PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
1
3.3 VOLT CMOS SyncBiFIFO
TM
64 x 36 x 2
IDT72V3612
1
JANUARY 2014
©2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-4659/5
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FEATURES:
••
••
• Two independent clocked FIFOs (64 x 36 storage capacity each)
buffering data in opposite directions
• Supports clock frequencies up to 83 MHz
••
••
•
Fast access times of 8ns
••
••
•
Free-running CLKA and CLKB can be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
• Mailbox bypass Register for each FIFO
• Programmable Almost-Full and Almost-Empty Flags
• Microprocessor interface control logic
• EFA , FFA , AEA , and AFA flags synchronized by CLKA
• EFB , FFB , AEB , and AFB flags synchronized by CLKB
• Passive parity checking on each port
• Parity generation can be selected for each port
• Available in space saving 120-pin thin quad flat package (TQFP)
• Green parts available, see ordering information
DESCRIPTION:
The IDT72V3612 is designed to run off a 3.3V supply for exceptionally low-
power consumption. This device is a monolithic high-speed, low-power CMOS
bi-directional clocked FIFO memory. It supports clock frequencies up to 83 MHz
and has read access times as fast as 8ns. The FIFO operates in IDT Standard
mode. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip
buffer data in opposite directions. Each FIFO has flags to indicate empty and
full conditions and two programmable flags (Almost-Full and Almost-Empty) to
FUNCTIONAL BLOCK DIAGRAM
Mail 1
Register
Input
Register
Output
Register
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Device
Control
RST
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
MBF1
4659 drw 01
Mail 2
Register
Write
Pointer
Read
Pointer
Status Flag
Logic
Parity
Gen/Check
A0 - A35
36
RAM
ARRAY
64 x 36
Parity
Generation
Parity
Gen/Check
Programmable Flag
Offset Register
Status Flag
Logic
Input
Register
Output
Register
RAM
ARRAY
64 x 36
Parity
Generation
Read
Pointer
PEFB
PGB
EFB
AEB
FFB
AFB
ODD/
EVEN
FFA
AFA
FS0
FS1
EFA
AEA
PGA
PEFA
MBF2
Write
Pointer
FIFO2
FIFO1
36
36
B0 - B36
2
IDT72V3612 3.3V, CMOS SyncBiFIFO
TM
64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
B
22
B
21
GND
B
20
B
19
B
18
B
17
B
16
B
15
B
14
B
13
B
12
B
11
B
10
GND
B
9
B
8
B
7
V
CC
B
6
B
5
B
4
B
3
GND
B
2
B
1
B
0
EFB
AEB
AFB
A
23
A
22
A
21
GND
A
20
A
19
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
GND
A
9
A
8
A
7
V
CC
A
6
A
5
A
4
A
3
GND
A
2
A
1
A
0
EFA
AEA
4659 drw 03
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
91
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
AFA
FFA
CSA
ENA
CLKA
W/RA
V
CC
PGA
PEFA
MBF
2
MBA
FS
1
FS
0
ODD/EVEN
RST
GND
NC
NC
NC
NC
MBB
MBF
1
PEFB
PGB
V
CC
W/RB
CLKB
ENB
CSB
FFB
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
B
23
A
24
A
25
A
26
V
CC
A
27
A
28
A
29
GND
A
30
A
31
A
34
A
35
B
35
GND
B
34
B
33
B
32
B
30
B
31
GND
B
29
B
28
B
27
V
CC
B
26
B
25
B
24
A
32
A
33
TQFP (PNG120, order code: PF)
TOP VIEW
NOTES:
1. Pin 1 identifier in corner.
2. NC - No internal connection.
PIN CONFIGURATION
indicate when a selected number of words is stored in memory. Communication
between each port can bypass the FIFOs via two 36-bit mailbox registers. Each
mailbox register has a flag to signal when new mail has been stored. Parity is
checked passively on each port and may be ignored if not desired. Parity
generation can be selected for data read from each port. Two or more devices
can be used in parallel to create wider data paths.
This device is a clocked FIFO, which means each port employs a
synchronous interface. All data transfers through a port are gated to the LOW-
to-HIGH transition of a port clock by enable signals. The clocks for each port
are independent of one another and can be asynchronous or coincident. The
enables for each port are arranged to provide a simple bi-directional interface
between microprocessors and/or buses with synchronous control.
The Full Flag (FFA, FFB) and Almost-Full (AFA, AFB) flag of a FIFO are
two-stage synchronized to the port clock that writes data to its array. The Empty
Flag (EFA, EFB) and Almost-Empty (AEA, AEB) flag of a FIFO are two stage
synchronized to the port clock that reads data from its array.
The IDT72V3612 is characterized for operation from 0
°
C to 70
°
C. This
device is fabricated using high speed, submicron CMOS technology.
3
IDT72V3612 3.3V, CMOS SyncBiFIFO
TM
64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE
Symbol Name I/O Description
A0-A35 Port A Data I/O 36-bit bidirectional data port for side A.
AEA Port A Almost-Empty O Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in
Flag (Port A) the FIFO2 is less than or equal to the value in the offset register, X.
AEB Port B Almost-Empty O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in
Flag (PortB) FIFO1 is less than or equal to the value in the offset register, X.
AFA Port A Almost-Full O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
Flag (Port A) locations in FIFO1 is less than or equal to the value in the offset register, X.
AFB Port B Almost-Full O Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty
Flag (Port B) locations in FIFO2 is less than or equal to the value in the offset register, X.
B0-B35 Port B Data. I/O 36-bit bidirectional data port for side B.
CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through port A and can be
asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the LOW-to-
HIGH transition of CLKA.
CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through port B and can be
asynchronous or coincident to CLKA. EFB, FFB, AFB, and AEB are synchronized to the LOW-to-
HIGH transition of CLKB.
CSA Port A Chip Select I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
The A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSB Port B Chip Select I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
EFA Port A Empty Flag O EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA is LOW, FIFO2 is empty,
(Port A) and reads from its memory are disabled. Data can be read from FIFO2 to the output register
when EFA is HIGH. EFA is forced LOW when the device is reset and is set HIGH by the second
LOW-to-HIGH transition of CLKA after data is loaded into empty FIFO2 memory.
EFB Port B Empty Flag O EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is LOW, the FIFO1 is
(Port B) empty, and reads from its memory are disabled. Data can be read from FIFO1 to the output
register when EFB is HIGH. EFB is forced LOW when the device is reset and is set HIGH by the
second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory.
ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FFA Port A Full Flag O FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is LOW, FIFO1 is full,
(Port A) and writes to its memory are disabled. FFA is forced LOW when the device is reset and is set
HIGH by the second LOW-to-HIGH transition of CLKA after reset.
FFB Port B Full Flag O FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB
is LOW, FIFO2 is full,
(Port B) and writes to its memory are disabled. FFB is forced LOW when the device is reset and is set
HIGH by the second LOW-to-HIGH transition of CLKB after reset.
FS1, FS0 Flag Offset Selects I The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which selects one of four
preset values for the Almost-Full flag and Almost-Empty flag.
MBA Port A Mailbox I A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the
Select A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output,
and a LOW level selects FIFO2 output register data for output.
MBB Port B Mailbox I A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
Select B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output,
and a LOW level selects FIFO1 output register data for output.
MBF1 Mail1 Register Flag O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-
HIGH transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is set HIGH
when the device is reset.
PIN DESCRIPTION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

72V3612L20PF

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IC FIFO 64X36X2 20NS 120QFP
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