72V3612L20PF Datasheet 72V3612L12PFG, 72V3612L15PF8, 72V3612L12PF8 | P10-P12

IDT72V3612 3.3V, CMOS SyncBiFIFO

64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE

and read operations and are not related to high-impedance control of the data

outputs. If a port enable is LOW during a clock cycle, the port chip select and

write/read select may change states during the setup and hold time window of

the cycle.

SYNCHRONIZED FIFO FLAGS

Each FIFO is synchronized to its port clock through two flip-flop stages.

This is done to improve flag reliability by reducing the probability of

metastable events on the output when CLKA and CLKB operate asynchro-

nously to one another. EFA, AEA, FFA, and AFA are synchronized by

CLKA. EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and

5 show the relationship of each port flag to the level of FIFO1 and FIFO2 fill.

EMPTY FLAGS (EFA, EFB)

The Empty Flag of a FIFO is synchronized to the port clock that reads

data from its array. When the Empty Flag is HIGH, new data can be read

to the FIFO output register. When the Empty Flag is LOW, the FIFO is empty

and attempted FIFO reads are ignored.

The read pointer of a FIFO is incremented each time a new word is

clocked to the output register. The state machine that controls an Empty

Flag monitors a write-pointer and read-pointer comparator that indicates

when the FIFO memory status is empty, empty+1, or empty+2. A word

written to a FIFO can be read to the FIFO output register in a minimum of

three cycles of the Empty Flag synchronizing clock. Therefore, an Empty

Flag is LOW if a word in memory is the next data to be sent to the FIFO output

not elapsed since the time the word was written. The Empty Flag of the FIFO

is set HIGH by the second LOW-to-HIGH transition of the synchronizing

clock, and the new data word can be read to the FIFO output register in the

following cycle.

A LOW-to-HIGH transition on an Empty Flag synchronizing clock begins

the first synchronization cycle of a write if the clock transition occurs at time

tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can

be the first synchronization cycle (see Figure 7 and Figure 8).

FULL FLAG (FFA, FFB)

The Full Flag of a FIFO is synchronized to the port clock that writes data

to its array. When the Full Flag is HIGH, a memory location is free in the

FIFO to receive new data. No memory locations are free when the Full Flag

is LOW and attempted writes to the FIFO are ignored.

Each time a word is written to a FIFO, the write pointer is incremented. The

state machine that controls a Full Flag monitors a write-pointer and read pointer

comparator that indicates when the FIFO memory status is full, full-1, or full-2.

Synchronized Synchronized

Number of Words to CLKB to CLKA

in the FIFO1

(1)

EFB AEB AFA FFA

0LLHH

1 to X H L H H

(X+1) to [64-(X+1)] H H H H

(64-X) to 63 H H L H

64 H H L L

Synchronized Synchronized

Number of Words to CLKB to CLKA

in the FIFO2

(1)

EFA AEA AFB FFB

0LLHH

1 to X H L H H

(X+1) to [64-(X+1)] H H H H

(64-X) to 63 H H L H

64 H H L L

NOTE:

1. X is the value in the Almost-Empty flag and Almost-Full flag offset register.

From the time a word is read from a FIFO, the previous memory location is ready

to be written in a minimum of three cycles of the Full Flag synchronizing clock.

Therefore, a Full Flag is LOW if less than two cycles of the Full Flag synchronizing

clock have elapsed since the next memory write location has been read. The

second LOW-to-HIGH transition on the Full Flag synchronization clock after the

read sets the Full Flag HIGH and the data can be written in the following clock

cycle.

A LOW-to-HIGH transition on a Full Flag synchronizing clock begins the

first synchronization cycle of a read if the clock transition occurs at time

tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can

be the first synchronization cycle (see Figure 9 and Figure 10).

ALMOST EMPTY FLAGS (AEA, AEB)

The Almost-Empty flag of a FIFO is synchronized to the port clock that

reads data from its array. The state machine that controls an Almost-Empty

flag monitors a write-pointer comparator that indicates when the FIFO

memory status is almost-empty, almost-empty+1, or almost-empty+2. The

almost-empty state is defined by the value of the Almost-Full and Almost-

Empty Offset register (X). This register is loaded with one of four preset

values during a device reset (see Reset section). An Almost-Empty flag is

LOW when the FIFO contains X or less words in memory and is HIGH when

the FIFO contains (X+1) or more words.

Two LOW-to-HIGH transitions of the Almost-Empty flag synchroniz-

ing clocks are required after a FIFO write for the Almost-Empty flag to reflect

the new level of fill. Therefore, the Almost-Empty flag of a FIFO containing

(X+1) or more words remains LOW if two cycles of the synchronizing clock

have not elapsed since the write that filled the memory to the (X+1) level.

An Almost-Empty flag is set HIGH by the second LOW-to-HIGH transition

of the synchronizing clock after the FIFO write that fills memory to the (X+1)

level. A LOW-to-HIGH transition of an Almost-Empty flag synchronizing

clock begins the first synchronization cycle if it occurs at time t

SKEW2 or

greater after the write that fills the FIFO to (X+1) words. Otherwise, the

subsequent synchronizing clock cycle can be the first synchronization cycle

(see Figure 11 and 12).

ALMOST FULL FLAGS (AFA, AFB)

The Almost-Full flag of a FIFO is synchronized to the port clock that

writes data to its array. The state machine that controls an Almost-Full flag

monitors a write-pointer and read-pointer comparator that indicates when the

FIFO memory status is almost-full, almost-full-1, or almost-full-2. The almost-full

state is defined by the value of the Almost-Full and Almost-Empty Offset register

(X). This register is loaded with one of four preset values during a device reset

(see Reset section). An Almost-Full flag is LOW when the FIFO contains (64-

TABLE 4 – FIFO1 FLAG OPERATION TABLE 5 – FIFO2 FLAG OPERATION

IDT72V3612 3.3V, CMOS SyncBiFIFO

64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE

X) or more words in memory and is HIGH when the FIFO contains [64-(X+1)]

or less words.

Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing

clock are required after a FIFO read for the Almost-Full flag to reflect the new

level of fill. Therefore, the Almost-Full flag of a FIFO containing [64-(X+1)]

or less words remains LOW if two cycles of the synchronizing clock have not

elapsed since the read that reduced the number of words in memory to

[64-(X+1)]. An Almost-Full flag is set HIGH by the second LOW-to-HIGH

transition of the synchronizing clock after the FIFO read that reduces the

number of words in memory to [64-(X+1)]. A second LOW-to-HIGH

transition of an Almost-Full flag synchronizing clock begins the first synchro-

nization cycle if it occurs at time tSKEW2 or greater after the read that reduces

the number of words in memory to [64-(X+1)]. Otherwise, the subsequent

synchronizing clock cycle can be the first synchronization cycle (see Figure

13 and 14).

MAILBOX REGISTERS

Each FIFO has a 36-bit bypass register to pass command and control

information between port A and port B without putting it in queue. The

Mailbox select (MBA, MBB) inputs choose between a mail register and a

FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA

writes A0-A35 data to the mail1 register when a port A write is selected by

CSA, W/RA, and ENA and MBA HIGH. A LOW-to-HIGH transition on CLKB

writes B0-B35 data to the mail2 register when a port B write is selected by

CSB, W/RB, and ENB and MBB is HIGH. Writing data to a mail register sets

the corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail

When a port's data outputs are active, the data on the bus comes from

the FIFO output register when the port Mailbox select input (MBA, MBB) is

LOW and from the mail register when the port mailbox select input is HIGH.

The Mail1 register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition

on CLKB when a port B read is selected by CSB, W/RB, and ENB and MBB

is HIGH. The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-HIGH

transition on CLKA when port A read is selected by CSA, W/RA, and ENA

and MBA is HIGH. The data in a mail register remains intact after it is read

and changes only when new data is written to the register. Mail register and

Mail Register Flag timing can be found in Figure 15 and Figure 16.

PARITY CHECKING

The port A inputs (A0-A35) and port B inputs (B0-B35) each have four

parity trees to check the parity of incoming (or outgoing) data. A parity failure

on one or more bytes of the input bus is reported by a LOW level on the port

Parity Error Flag (PEFA, PEFB). Odd or even parity checking can be selected,

and the Parity Error Flags can be ignored if this feature is not desired.

Parity status is checked on each input bus according to the level of the

Odd/Even parity (ODD/EVEN) select input. A parity error on one or more bytes

of a port is reported by a LOW level on the corresponding port Parity Error

Flag (PEFA, PEFB) output. Port A bytes are arranged as A0-A8, A9-A17, A18-

A26, and A27-A35 with the most significant bit of each byte used as the parity

bit. Port B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35, with

the most significant bit of each byte used as the parity bit. When odd/even parity

is selected, a port Parity Error Flag (PEFA, PEFB) is LOW if any byte on the

port has an odd/even number of LOW levels applied to the bits.

The four parity trees used to check the A0-A35 inputs are shared by the

mail2 register when parity generation is selected for port A reads (PGA = HIGH).

When a port A read from the mail2 register with parity generation is selected with

W/RA LOW, CSA LOW, ENA HIGH, MBA HIGH, and PGA HIGH, the port A

Parity Error Flag (PEFA) is held HIGH regardless of the levels applied to the

A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are

shared by the mail1 register when parity generation is selected for port B reads

(PGB = HIGH). When a port B read from the mail1 register with parity generation

is selected with W/RB LOW, CSB LOW, ENB HIGH, MBB HIGH, and PGB HIGH,

the port B Parity Error Flag (PEFB) is held HIGH regardless of the levels applied

to the B0-B35 inputs (see Figure 17 and Figure 18).

PARITY GENERATION

A HIGH level on the port A Parity Generate select (PGA) or port B

Parity Generate select (PGB) enables the IDT72V3612 to generate parity

bits for port reads from a FIFO or mailbox register. Port A bytes are arranged

as A0-A8, A9-A17, A18-26, and A27-A35, with the most significant bit of

each byte used as the parity bit. Port B bytes are arranged as B0-B8, B9-

B17, B18-B26, and B27-B35, with the most significant bit of each byte used

as the parity bit. A write to a FIFO or mail register stores the levels applied

to all thirty-six inputs regardless of the state of the Parity Generate select

(PGA, PGB) inputs. When data is read from a port with parity generation

selected, the lower eight bits of each byte are used to generate a parity bit

according to the level on the ODD/EVEN select. The generated parity bits

are substituted for the levels originally written to the most significant bits of

each byte as the word is read to the data outputs.

Parity bits for FIFO data are generated after the data is read from

SRAM and before the data is written to the output register. Therefore, the

port A Parity Generate select (PGA) and Odd/Even parity select (ODD/

EVEN) have setup and hold time constraints to the port A Clock (CLKA) and

the port B Parity Generate select (PGB) and ODD/EVEN have setup and

hold-time constraints to the port B Clock (CLKB). These timing constraints

only apply for a rising clock edge used to read a new word to the FIFO output

The circuit used to generate parity for the mail1 data is shared by the

port B bus (B0-B35) to check parity and the circuit used to generate parity

for the mail2 data is shared by the port A bus (A0-A35) to check parity. The

shared parity trees of a port are used to generate parity bits for the data in

a mail register when the port Write/Read select (W/RA, W/RB) input is LOW,

the port Mail select (MBA, MBB) input is HIGH, Chip Select (

CSA, CSB) is

LOW, Enable (ENA, ENB) is HIGH, and port Parity Generate select (PGA,

PGB) is HIGH. Generating parity for mail register data does not change the

contents of the register (see Figure 19 and Figure 20).

IDT72V3612 3.3V, CMOS SyncBiFIFO

64 x 36 x 2 COMMERCIAL TEMPERATURE RANGE

Figure 2. Device Reset and Loading the X Register with the Value of Eight

CLKA

RST

FFA

FFB

EFB

AEA

CLKB

EFA

FS1,FS0

4659 drw 05

RSTS

RSTH

FSH

FSS

WFF

0,1

REF

PAE

PAF

AFA

MBF1,

MBF2

AEB

AFB

RSF

PAE

PAF

WFF

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

72V3612L20PF

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72V3612L20PF

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